Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-06-28
2002-06-04
Weiss, Howard (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S014000, C438S108000, C257S738000, C257S778000
Reexamination Certificate
active
06399474
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the testing of integrated circuits, and in particular, to the preparation of a chip scale package prior to electrical characterization of the package.
DESCRIPTION OF RELATED ART
Electrical components utilizing integrated circuit chips are used in a number of applications. Controlled Collapsed Chip Connection is an interconnect technology developed as an alternative to wire bonding. This technology is generally known as C4 technology, or flip chip packaging. Broadly stated, one or more integrated circuit chips are mounted above a single or multiple layer substrate and pads on the chip are electrically connected to corresponding pads on a substrate by a plurality of electrical connections, such as solder bumps. The integrated circuit chips may be assembled in an array such as a 10×10 array. A substrate is then electrically connected to another electronic device such as a circuit board with the total package being used in an electronic device such as a computer.
It is desirable to perform an electrical characterization of an integrated circuit by measuring inductance (L), capacitance (C), and resistance (R) at electrical contacts of the integrated circuit. This has presented a problem, however, when measuring these parameters for a “chip scale package.” Semiconductor dice, or chips, are typically individually packaged for use in plastic or ceramic packages. This is sometime referred to as the first level of packaging. The package is required to support, protect, and dissipate heat from the die and to provide a lead system for power and signal distribution to the die. The package is also useful for performing burn-in and functionality testing of the die.
One type of semiconductor package is referred to as a “chip scale package.” Chip scale packages are also referred to as “chip size packages,” and the dice are referred to as being “minimally packaged.” Chip scale packages can be fabricated in “uncased” or “cased” configurations. Uncased chip scale packages have a footprint that is about the same as an unpackaged die. Cased chip scale packages have a peripheral outline that is slightly larger than an unpackaged die. For example, a footprint for a typical cased chip scale package can be about 1.2 times the size of the die contained within the package.
Typically, a chip scale package includes a substrate bonded to the face of the die. The substrate includes the external contacts for making outside electrical connections to the chip scale package. The substrate for a chip scale package can comprise flexible material, such as a polymer tape, or a rigid material, such as silicon, ceramic, or glass. The external contacts for one type of chip scale package includes solder balls arranged in a dense array, such as a ball grid array “BGA,” or a fine ball grid array “FBGA.” These dense arrays permit a high input/output capability for the chip scale package. For example, a FBGA on a chip scale package can include several hundred solder balls.
In order to test the electrical characteristics of the integrated circuit, test probes are used to contact individual solder balls. Performing precise measurements of the electrical characteristics on a chip scale package is very difficult, however, due to the dimensions. It is hard to isolate a single solder ball or other electrical contact, while grounding the remainder of the solder balls. Hence, isolation and testing of a single, selected solder ball of an integrated circuit has proven to be a difficult task.
One of the reasons for the problems in performing electrical characterization of a chip scale package is the difficulty of simultaneously grounding all of the solder balls that are to be grounded on the package. Even with modern sophisticated manufacturing techniques, the solder balls of a ball grid array on a chip scale package will typically have heights that are slightly different from one another. It is possible to simultaneously ground all of the solder balls of a ball grid array with a flat conductive plate placed against the solder balls, but only if the conductive plate contacts each one of the balls. This can occur if the solder balls are the same height, but is problematic when the balls are of different heights, as the conductive plate will contact only the highest solder balls.
SUMMARY OF THE INVENTION
There is a need for a method and apparatus for preparing a chip scale package to allow simultaneous contact of all of the solder balls of a ball grid array during electrical characterization of the package, even when the solder balls are manufactured with different heights on the package.
This and other needs are met by the present invention which provides a method of preparing and testing electrical characteristics of a chip scale package that has a plurality of solder balls with solder ball tops and solder ball bottoms attached to a surface of the package. The method comprises planarizing the tops of the plurality of solder balls such that the solder balls extend the same distance in a normal direction from the package surface. A conductive plate is placed on the chip scale package such that the conductive plate contacts the top of each of the plurality of solder balls, except for a selected subset of the solder balls. The conductive plate is grounded to thereby ground all of the solder balls except for the selected subset. The selected subset of solder balls, i.e., those not grounded, are exposed to allow testing of the electrical characteristics at the selected subset.
In certain embodiments of the invention, the planarizing involves applying a heated pressing plate having a smooth, flat bottom surface against the tops of the solder balls. The heating and pressing is continued with a controlled pressure until a portion of the top of each of the solder balls are coplanar.
The planarizing of the solder balls before electrical characterization testing (i.e., “precoining”) in accordance with embodiments of the invention, provides a planar surface against which a flat grounding plate can be placed. It is thus assured that each of the solder balls will reliably make electrical contact with the grounding plate, even if the solder balls were initially of different heights. The use of a heated plate, in accordance with certain embodiments of the invention, allows a relatively gentle pressure to be applied against the solder balls to flatten the highest solder balls. This is advantageous over hard pressing of the solder balls, since it is possible to damage the solder balls through such a technique.
The foregoing and other features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5435482 (1995-07-01), Variot et al.
patent: 6084781 (2000-07-01), Klein
Advanced Micro Devices , Inc.
Sutton Timothy
Weiss Howard
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