Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-06-29
2002-08-06
Weiss, Howard (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S382000, C257S401000
Reexamination Certificate
active
06429480
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same and, more particularly, to a semiconductor device having a MOS (Metal-Oxide-Semiconductor) nonvolatile memory cell with a floating gate electrode, and a MOS field effect transistor (to be referred to as a MOS transistor hereinafter), and a method of manufacturing the same.
2. Description of the Prior Art
In general, a semiconductor device incorporating a nonvolatile memory and a logic circuit (e.g., circuit having a nonvolatile memory control function) on one chip comprises, on a semiconductor substrate, a MOS nonvolatile memory cell (to be simply referred to as a memory cell hereinafter) with a multilayered gate structure of floating and control gate electrodes, and a MOS transistor operating as a logic circuit element.
FIGS. 1A
to
1
F show an example of a method of manufacturing a conventional semiconductor device having a nonvolatile memory cell and a MOS transistor.
As shown in
FIG. 1A
, silicon oxide element isolation regions
102
are formed in the surface region of a silicon substrate
101
. The element isolation regions
102
demarcate many active regions in the surface region of the silicon substrate
101
in both a memory cell region A
101
where memory cells are going to be formed and a logic circuit region A
102
where MOS transistors are going to be formed. For descriptive convenience, single active regions are formed in the memory cell and logic circuit regions A
101
and A
102
, respectively.
A silicon oxide film (not shown) is formed on the entire surface of the silicon substrate
101
, and a doped polysilicon film (not shown) is deposited on the silicon oxide film. The silicon oxide film and the polysilicon film are simultaneously patterned into a predetermined shape to form a tunnel insulating film
103
and a floating gate electrode
104
in the memory cell region A
101
on the silicon substrate
101
.
As shown in
FIG. 1B
, a silicon oxide film and a doped polysilicon film (neither is shown) are sequentially deposited to cover the entire silicon substrate
101
, and patterned into the same shape as the floating gate electrode
104
, thereby forming an internal insulating film
105
and a control gate electrode
106
on the floating gate electrode
104
. At this time, a deposited silicon oxide film
107
and a polysilicon film
108
remain in the logic circuit region A
102
on the silicon substrate
101
.
As shown in
FIG. 1C
, the silicon oxide film
107
and the polysilicon film
108
are simultaneously patterned into a predetermined shape to form a gate insulating film
109
and a gate electrode
110
in the logic circuit region A
102
.
As shown in
FIG. 1D
, a silicon oxide film (not shown) is deposited to cover the entire silicon substrate
101
, and then etched back to form a pair of silicon oxide sidewall spacers
112
A on the sides of the floating and control gate electrodes
104
and
106
, and a pair of silicon oxide sidewall spacers
112
B on the sides of the gate electrode
110
.
Subsequently, impurity ions are implanted into the surface region of the silicon substrate
101
using the control gate electrode
106
, gate electrode
110
, and sidewall spacers
112
A and
112
B as a mask. This ion implantation forms a pair of source and drain regions
111
A in the memory cell region A
101
, and a pair of source and drain regions
111
B in the logic circuit region A
102
.
As a result, a MOS memory cell
121
made up of the pair of source and drain regions
11
A, tunnel insulating film
103
, floating gate electrode
104
, internal insulating film
105
, and control gate electrode
106
is formed in the memory cell region A
101
. A MOS transistor
122
made up of the pair of source and drain regions
111
B, gate insulating film
109
, and gate electrode
110
is formed in the logic circuit region A
102
.
As shown in
FIG. 1E
, silicon oxide is deposited to cover the entire silicon substrate
101
, thereby forming an interlevel insulating film
113
. Then, the surface of the interlevel insulating film
113
is planarized. The interlevel insulating film
113
is selectively etched using a patterned photoresist film as a mask, thereby forming contact holes
114
and
115
extending through the interlevel insulating film
113
. The bottoms of the contact holes
114
and
115
reach the control gate electrode
106
and one source/drain region
111
B, respectively.
As shown in
FIG. 1F
, a tungsten film (not shown) is deposited on the interlevel insulating film
113
to a thickness enough to completely fill the internal spaces of the contact holes
114
and
115
. This tungsten film is patterned into a predetermined shape, thereby forming interconnection layers
116
and
117
.
In this manner, a conventional semiconductor device in which the memory cell
121
and the MOS transistor
122
are formed on the silicon substrate
101
is completed.
In the conventional semiconductor device manufacturing method shown in
FIGS. 1A
to
1
F, the control gate electrode
106
of the memory cell
121
and the gate electrode
110
of the MOS transistor
122
are formed by patterning identical polysilicon films. However, patterning the polysilicon film is separately performed for the control gate electrode
106
and the gate electrode
110
. The polysilicon films cannot be patterned at once because the memory cell
121
and the MOS transistor
122
are different in design rule. That is, the MOS transistor
122
has a finer structure than the memory cell
121
. Since the memory cell
121
has the multilayered gate structure of the floating and control gate electrodes
104
and
106
, the gate electrode
110
cannot be formed prior to formation of the floating gate electrode
104
. For this reason, the manufacturing process concerning formation of the MOS transistor
122
must be greatly changed, which makes it difficult to share the manufacturing process and the manufacturing equipment. Hence, the manufacturing cost increases.
When the memory cell
121
is micropatterned for high integration degree, the planar shapes of the control and floating gate electrodes
106
and
104
are downsized. Accordingly, the overlapping area between the control and floating gate electrodes
106
and
104
decreases to decrease the electrostatic capacitance. A small electrostatic capacitance between the control and floating gate electrodes
106
and
104
decreases the capacitive coupling ratio (ratio of the electrostatic capacitance between the control and floating gate electrodes
106
and
104
to that between the floating gate electrode
104
and the silicon substrate
101
). This makes it difficult to transfer a voltage applied to the control gate electrode
106
to a channel region formed between the pair of source and drain regions
11
A. This increases the driving voltage.
SUMMARY OF THE INVENTION
The present invention has been made in consideration of the above situation, and has as its first object to provide a semiconductor device in which the manufacturing process and the manufacturing equipment can be easily shared to reduce the manufacturing cost, and a method of manufacturing the same.
It is the second object of the present invention to provide a semiconductor device capable of forming a nonvolatile memory cell without greatly changing the manufacturing process concerning a field effect transistor, and a method of manufacturing the same.
It is the third object of the present invention to provide a semiconductor device capable of incorporating a nonvolatile memory cell that can be driven by a low voltage, and a method of manufacturing the same.
To achieve the first and second objects, according to the first aspect of the present invention, there is provided a semiconductor device in which a nonvolatile memory cell with a floating gate electrode and a field effect transistor are formed on a semiconductor substrate, comprising
a first conductive layer which is formed on the semiconductor substrate via a tunnel insulating film, and
Pizarro-Crespo Marcos D.
Weiss Howard
Young & Thompson
LandOfFree
Semiconductor device having nonvolatile memory cell and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device having nonvolatile memory cell and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device having nonvolatile memory cell and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2963133