Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-05-03
2002-11-26
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S369000, C257S296000, C257S297000, C257S298000, C257S299000, C257S300000, C257S344000, C257S371000, C257S382000, C257S383000, C257S384000, C257S900000, C257S903000
Reexamination Certificate
active
06486516
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of producing the same, in particular to, a semiconductor device having a semiconductor substrate, on which both of a memory device and a logic device are formed, hereinbelow referred to as a logic process consolidating device, and a method of producing the semiconductor device.
2. Discussion of Background
In recent years, it is required that semiconductor devices are formed to be a single chip in response to an age of multimedia. For example, a memory device such as a dynamic random access memory (DRAM), a static random access memory (SRAM), and a flash memory, and a logic device are formed on a single semiconductor substrate and mounted on a single chip.
FIG. 24
is a cross-sectional view illustrating a structure of a conventional logic process consolidating DRAM. In
FIG. 24
, numerical reference
100
designates a memory device region; and numerical reference
101
designates a logic device region. Hereinbelow, the structure of the conventional logic process consolidating DRAM will be described in reference of FIG.
24
.
A cross-sectional structure of the memory device region of the conventional logic process consolidation DRAM will be described. In the memory device region, an active region formed by a bottom n-well
52
and a p-well region
53
a
formed on a bottom n-well
52
is located on a silicon substrate
51
. On a principle surface of the silicon substrate
51
, an isolating region
54
and a gate oxide film
55
are formed. On the p-well region
53
a
surrounded by the isolating region
54
has source/drain areas
56
a
,
56
b.
On the gate oxide film
55
and an isolating oxide film
54
, gate electrodes
57
a
through
57
c
are formed with a predetermined interval. On upper surfaces of the gate electrodes
57
a
through
57
c
, for example, an insulating film
58
made of a silicon nitride film or a TEOS oxide film is formed. Further, a silicon oxide film
59
is formed on the insulating film
58
, the source/drain areas
56
a
,
56
b
, and the isolating region
54
so as to cover these. A silicon nitride film
60
is formed so as to cover an upper surface of the silicon oxide film
59
. Further, an inter-layer insulating film
67
is formed to cover the silicon nitride film
60
.
Above the source/drain area
56
b
, the inter-layer insulating film
67
, the silicon nitride film
60
, the silicon oxide film
59
, a part of the insulating film
58
formed on the gate electrodes
57
b
and
57
c
, and a self-alignment contact opening
69
for exposing the gate oxide film
55
are formed. The self-alignment contact opening
69
is formed to expose a surface of the source/drain area
56
b.
A plug made of a conductive material and so on is formed in the self-alignment contact opening
69
. Such a plug is used as a contact for, for example, a storage node contact of a bit wire or a capacitor cell. After forming the plug, a lower electrode (not shown) of a bit wire or a capacitor is formed. The lower electrode of a bit wire or the capacitor is electrically connected to the source/drain area
56
b
through the plug.
Meanwhile, in the logic device region, the isolating region
54
is formed on a principle surface of the silicon substrate
51
. Further, on the active region surrounded by the isolating region
54
, the n-well region
53
b
and the p-well region
53
c
are respectively formed. In the n-well region
53
b
, low concentration impurity regions
56
c
,
56
d
and high concentration impurity regions
62
c
,
62
d
are formed, whereby source/drain regions
70
c
,
70
d
having a lightly doped drain (LDD) structure are configurated.
Further, in the p-well region
53
c
of the silicon substrate
51
, low concentration impurity regions
56
e
,
56
f
and high concentration impurity regions
62
a
,
62
b
are formed, whereby source/drain areas
70
a
,
70
b
having a LDD structure are configurated. On a channel region between source/drain areas
70
c
and
70
d
, a gate electrode
57
d
is formed through a gate oxide film
55
. Further, in the p-well region
53
c
, a gate electrode
57
e
is formed through the gate oxide film
55
.
The insulating film
58
made of a silicon nitride film or a TEOS oxide film is formed respectively on upper surfaces of the gate electrodes
57
d
and
57
e
. A side wall made of the silicon oxide film
59
and the silicon nitride film
60
is formed so as to be in contact with side surfaces of the gate electrode
57
d
and the insulating film
58
. In a similar manner, a side wall made of the silicon oxide film
59
and the silicon nitride film
60
is formed so as to be in contact with side surfaces of the gate electrode
57
e
and the insulating film
58
.
A silicide protection film
64
is formed to cover parts respectively of the insulating film
58
formed on the upper surface of the gate electrode
57
d
, a surface of the side wall, and the source/drain areas
62
c
,
62
d
. On the source/drain areas
70
a
through
70
d
without the silicide protection film
64
, a high-melting metallic silicide film
66
made of, for example, a cobalt silicide film, a titanium silicide film, and so on is formed. The inter-layer insulating film
67
is formed above an entire surface of the semiconductor substrate
51
.
In the conventional logic process consolidating device, a conduction type of the active region and a conduction type of the impurities to be implanted are not limited to those described above, and adverse conduction types may be used.
In the next, in reference of
FIGS. 13 through 24
, a method of producing the conventional logic process consolidating device will be described. In
FIG. 13
, the isolating region
54
is formed on the principle surface of the silicon substrate
51
, in which the bottom n-well
52
, the p-well region
53
a
, the n-well region
53
b
and the p-well region
53
c
are formed. A structure of isolating of the isolating region
54
is obtained by opening a deep groove in the silicon substrate
51
, and embedding an insulating film such as an oxide film in use of a Shallow Trench Isolation (STI) process, whereby the structure of isolation becomes flat.
The gate oxide film
55
is formed on the principle surface of the silicon substrate
51
. In a predetermined area on the gate oxide film
55
or the isolating oxide film
54
, the gate electrodes
57
a
through
57
e
are formed. An n-type impurity is implanted in the p-well regions
53
a
,
53
c
in the silicon substrate
51
by ion implantation. A p-type impurity is implanted in the n-well
53
b
in the silicon substrate
51
by ion implantation. Thus, the source/drain areas
56
a
,
56
b
and the low concentration impurity regions
56
c
through
56
f
are formed. As illustrated in
FIG. 14
, the silicon oxide film
59
is formed above the entire surface of the silicon substrate
51
so as to cover the gate electrodes
57
a
through
57
e
and the insulating film
58
formed thereon. The silicon nitride film
60
is formed on the silicon oxide film
59
. As illustrated in
FIG. 15
, a resist
61
is coated, and an n-type transistor area in the logic device region is opened by photoengraving.
In the next, the silicon oxide film
59
and the silicon nitride film
60
are subjected to anisotropic etching to form side walls on both sides of the gate electrode
57
e
. An n-type impurity is further implanted in a self-replicating manner using the side walls and so on as a mask to form the high concentration impurity regions
62
a
,
62
b
. The source/drain area
70
a
having the LDD structure is configurated by the low concentration impurity region
56
e
and the high concentration impurity region
62
a
. Further, the source/drain area
70
b
having the LDD structure is configurated by the low concentration impurity region
56
f
and the high concentration impurity region
62
b.
As illustrated in
FIG. 16
, the resist
63
is coated, and the p-type transistor region in the logic device region is opened by photoengraving. Succeedingly, the s
Flynn Nathan J.
Mitsubishi Denki & Kabushiki Kaisha
Sefer Ahmed N.
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