Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-12-19
2002-11-05
Meeks, Timothy (Department: 1762)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S627000, C438S629000, C438S631000, C438S632000, C438S633000, C438S646000, C438S650000, C438S686000, C438S687000, C438S692000, C427S250000
Reexamination Certificate
active
06475900
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a metal interconnection; and, more particularly, to the method for manufacturing the metal interconnection with enhanced filling capability by forming a protection layer on a diffusion barrier layer using a damascene process.
DESCRIPTION OF THE PRIOR ART
With a high integration of a semiconductor device, a copper interconnection is being applied to the device due to its low electrical resistance. For employing the copper interconnection in the semiconductor device, a damascene process is used because dry-etching process is hardly applied to deposit the copper interconnection.
Referring to
FIGS. 1A
to
1
D, there are provided cross sectional views setting forth a conventional method for manufacturing the copper interconnection by using a damascene process.
The manufacturing steps begin with a preparation of active matrix
110
provided with a conductive layer
112
. After this, an insulating layer
114
is formed on top of the conductive layer
112
and then, patterned into a predetermined configuration by using a damascene process, thereby obtaining an opening
116
. Thereafter, a diffusion barrier layer
118
, e.g., made of titanium/titanium nitride (Ti/TiN), is formed on entire surface including the opening
116
for preventing a penetration of copper atoms into the insulating layer
114
.
In a next step as shown in
FIG. 1B
, a first copper layer
120
is formed on the diffusion barrier layer
118
by using a method such as a physical vapor deposition (PVD) technique at a room temperature.
In a subsequent step as shown in
FIG. 1C
, a second copper layer is formed on the first copper layer
120
for reflowing copper into the opening
116
by using the PVD technique at a high temperature, thereby obtaining a copper layer
120
A. While depositing copper at the high temperature by the PVD technique, the first copper layer
120
reacts with the diffusion barrier layer
118
, thereby forming an intermetallic compound
118
A. That is, if the diffusion barrier layer is made of Ti/TiN layer, Cu
3
Ti intermetallic compound is formed between the first copper layer
120
and the diffusion barrier layer
118
. The intermetallic compound
118
A has a large grain size of Cu
3
Ti to cause a bad gap-fill property. That is, owing to the large grain size of the intermetallic compound
118
A, it plays a role in preventing an adequate deposition in a bottom portion of the opening
116
. Thus, a copper layer
120
A with a predetermined thickness is formed only over the opening
116
so that there is happened a void
122
between the copper layer
120
A and a copper layer
120
C, as shown in FIG.
1
C.
Finally, a copper layer is polished back to a top surface of the insulating layer, thereby a copper interconnection
120
B being remained within the opening
116
as shown in FIG.
1
D. Polishing back of the copper layer is accomplished by a chemical mechanical polishing (CMP) technique.
As described above, when the second copper layer is formed at the high temperature after forming the first copper layer at the room temperature, an intermetallic compound having the large grain size may occur on the surface of the diffusion barrier layer.
Therefore, the second copper layer cannot be deposited on sidewalls of the opening so that the void is happened therein and the filling capability is deteriorated. And further, this makes the resistance of the copper interconnection increased and causes a reliability problem of the device at last.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a method for manufacturing a copper interconnection with an enhanced filling capability by using a protection layer after forming a diffusion barrier layer using a damascene process.
In accordance with one aspect of the present invention, there is provided a method for manufacturing a metal interconnection, the method comprising the steps of: a) preparing an active matrix provided with a substrate, an insulating layer and an opening formed through the insulating layer; b) forming a diffusion barrier layer on surfaces of the opening and the insulating layer; c) forming a protection layer on the diffusion barrier layer; d) forming a first metal layer into the opening and upon the protection layer; e) forming a second metal layer on the first metal layer; and f) polishing back the first and the second metal layer to a top surface of the insulating layer, thereby forming a metal interconnection.
REFERENCES:
patent: 6090701 (2000-07-01), Hasunuma et al.
patent: 6249055 (2001-06-01), Dubin
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Hyundai Electronics Industries Co,. Ltd.
Meeks Timothy
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