Domed wafer reactor vessel window with reduced stress at...

Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching

Reexamination Certificate

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Details

C438S710000, C438S714000, C118S715000, C118S724000

Reexamination Certificate

active

06436837

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to thermal reactors for processing semiconductor wafers, and more particularly to a reactor having a domed window with reduced stress at atmospheric and above atmospheric pressure processes.
BACKGROUND OF THE INVENTION
Recent technological progress is closely identified with the increasing miniaturization of electronic circuits made possible by advances in semiconductor processing. Certain advanced processing techniques require exposing a semiconductor structure to a reactant gas under carefully controlled conditions. Examples of such processes include chemical vapor deposition-etching processes. Of particular concern is the uniformity of temperature and gas flow to ensure uniform results, e.g., deposition thickness, across a wafer.
The process of depositing layers on a semiconductor wafer (or substrate) usually involves placing the substrate within a thermal reactor chamber and holding the wafer within a stream of a reactant gas flowing across the surface of a wafer. The thermal reactor is heated by external lamps which pass infra-red radiation into the reactor chamber through heating ports. The heating ports are covered by quartz windows that are transparent to the infra-red radiation.
Prior art deposition processes involve the deposition of a reactant gas at ambient and subambient pressures.
FIG. 1
illustrates a cross-sectional view of a thermal reactor
100
used for reduced pressure operations. Reactor
100
includes a chamber
102
for facilitating the flow of a process gas over the surface of a wafer. The housing includes a baseplate
104
having a gas inlet port
106
and a gas exhaust port
108
. An upper clamp ring
110
and a lower clamp ring
112
act to hold a quartz cover member
114
and a quartz lower member
116
in place, respectively. Cover member
114
generally includes a flange portion
118
and a central window portion
120
. Flange portion
118
is resiliently supported between baseplate
104
and clamp ring
110
by resilient o-rings
122
. Process gas is injected into chamber
102
through gas inlet port
106
which is connected to a gas source. Residual process gas and various waste products are continuously removed from the interior of chamber
102
through exhaust port
108
. A susceptor
124
holds the wafer in position during the semiconductor/layer deposition process. A susceptor support shaft
126
is coupled to susceptor
124
for positioning and rotating the wafer during the semiconductor fabrication process. Quartz central window portion
120
has an outward bow that forms a convex outside surface. The outward bow is curved enough to oppose the compressive force of the ambient pressure against the reduced internal pressure of chamber
102
during wafer processing. Heating lamps
128
and
130
provide infra-red radiant heat into the chamber through window portion
120
and quartz lower member
116
which are transparent to infra-red radiation.
Wafer processing at ambient pressure is often desired because the deposition rate of the process gas is higher at ambient pressure than it is at a reduced pressure. Ambient pressure processing also allows the use of certain chemical species, for example, trichlorosilane, which has an undesirable effect of coating the chamber walls at reduced pressures.
FIG. 2
illustrates a cross-sectional view of an ambient pressure thermal reactor
200
. As shown in
FIG. 2
, reactor
200
contains a flat quartz window
202
in lieu of the outwardly bowed window of the subambient pressure reactor of FIG.
1
. Although the flat window provides a uniform reactant gas flow across the surface of the wafer, it cannot be used in processing applications wherein a differential pressure exists across the surface of the window. When subjected to chamber over pressure or under pressure situations the differential pressure across the flat window causes localized stresses to occur that subject the window to breakage. Another problem associated with the flat window design is that high internal tensile stresses resulting from temperature gradients within the window may result in breakage.
One way to overcome these problems is to increase the wall thickness of the window. However, this produces an undesirable result in that the interior surface temperature of the quartz increases as the wall thickness increases. This increase in temperature can lead to deposition on the interior surface of the quartz window, which, in turn, reduces the radiant heat transfer through the window.
SUMMARY OF THE INVENTION
A thermal reactor for processing a semiconductor wafer is disclosed. The thermal reactor vessel contains a cover member having a central quartz window portion having an inward bow defining a concave outside surface. The unique shape of the quartz window permits the operating pressure of the thermal reactor chamber to be maintained at a pressure greater than atmospheric pressure. The positive chamber pressure reduces the stress level in the heated cover member by compensating for the stress produced by the thermal expansion produced during heating of the thermal reactor. Thus, in accordance with the present invention the deposition of a layer onto the surface of a wafer may be achieved by mounting the wafer on a susceptor within the chamber and pressurizing the chamber above atmospheric pressure with a processing reactant gas. Once the chamber is pressurized, the wafer is heated by radiating heat through the quartz central window portion and a reactant gas is introduced into chamber to flow over the wafer.


REFERENCES:
patent: 4920918 (1990-05-01), Adams et al.
patent: 5085887 (1992-02-01), Adams et al.
patent: 5108792 (1992-04-01), Anderson et al.
patent: 5194401 (1993-03-01), Adams et al.
patent: 5234526 (1993-08-01), Chen et al.
patent: 5385633 (1995-01-01), Russell et al.
patent: 5587019 (1996-12-01), Fujie
patent: 5690781 (1997-11-01), Yoshida et al.
patent: 393809 (1990-01-01), None
patent: 474251 (1991-06-01), None
Single Wafer RTP-CVD Epitaxial Deposition Technology, Fred Wong pp. 53-54 400 Solid State Technology 32 (1989) Oct., No. 10, Tulsa, OK. US.

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