Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-07-26
2002-11-12
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06480999
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to programmable logic devices (PLDs), and more particularly to a method for routing signals in programmable logic devices.
BACKGROUND OF THE INVENTION
A programmable logic device, such as a field programmable gate array (FPGA), is designed to be user-programmable so that users can implement logic designs of their choices. In a typical architecture, an FPGA includes an array of configurable logic blocks (CLBs) surrounded by programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a hierarchy of programmable routing resources. These CLBs, IOBs, and programmable routing resources are customized by loading a configuration bitstream into the FPGA.
When an FPGA comprises thousands of CLBs in large arrays of tiles, the task of establishing the required multitude of interconnections between primitive cells inside a CLB and between the CLBs becomes so onerous that it requires software tool implementation. Accordingly, the manufacturers of FPGAs, including the assignee hereof, Xilinx, Inc., have developed place and route software tools which may be used by their customers to implement their respective designs into the FPGAs of these manufacturers.
The execution of routing software (called herein “router engines”) can be very time consuming. A typical design implementation can take many hours of computer time using conventional routing software tools. Many routing methods do not connect resources optimally. This could lead to unnecessary timing delays and power consumption in the final design. Thus, there is a need to improve conventional routing methods.
SUMMARY OF THE INVENTION
The present invention involves a novel application of area constraint for signal routing in a programmable logic device. The method of the present invention can be applied to designs that can be separated into global logic and a number of modules. The signals of the design include at least one global signal and a plurality of local signals. Each local signal is associated with at least one of the modules. The local signals are area constrained. During the module implementation phase of the present invention, an area constraint property is attached to each local signal, while the global signal is not attached to an area constraint property. In one embodiment, power and ground signals are also associated with area constraint properties during this module implementation phase. The global signal is not pre-routed and locked. A router engine routes all the signals in each module under the restrictions of their respective area constraint properties. Thus, the router engine does not commit to a sub-optimal solution. It avoids pre-routing and locking of results early in the routing process.
During the assembly phase, the global logic and the modules are merged into a single design. During this phase, area constraint is removed from the power and ground signals. The modules implemented under the module implementation phase are retrieved. As each module is retrieved, its routing is not considered locked. Instead, the router engine has the freedom to rip-up and re-route the signals. However, the routing performed under module implementation is normally kept unless it leads to conflicts or it contains signals running across other modules. This process allows the router engine to explore alternative allowable routing solutions to better achieve overall optimal solution for the entire design.
The above summary of the present invention is not intended to describe each disclosed embodiment of the present invention. The figures and detailed description that follow provide additional example embodiments and aspects of the present invention.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1A
is a flow chart showing a modular design process of the present invention.
FIG. 1B
is a flow chart showing detailed steps of module implementation of the present invention.
FIG. 1C
is a flow chart showing detailed steps of the assembly phase of the present invention.
FIG. 2A
is a flow chart showing the detailed steps of area constraint property assignment in accordance with the present invention.
FIG. 2B
is a flow chart showing the detailed steps of signal routing in the module implementation phase of the present invention.
FIG. 3
is a flow chart showing the detailed steps of routing in the assembly phase of the present invention.
REFERENCES:
patent: 5544066 (1996-08-01), Rostoker et al.
patent: 6145117 (2000-11-01), Eng
patent: 6269467 (2001-07-01), Chang et al.
patent: 6360356 (2002-03-01), Eng
XAPP404 (v1.2) Application Note entitled “Xilinx Alliance 3.1i Modular Design”; Apr. 20, 2001; available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124; pp. 1-25.
Kalman Sandor S.
Kong Raymond
Chan H. C.
Dinh Paul
Smith Matthew
Xilinx , Inc.
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