Semiconductor device manufacturing: process – Semiconductor substrate dicing – Having specified scribe region structure
Reexamination Certificate
2001-05-31
2002-10-08
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Semiconductor substrate dicing
Having specified scribe region structure
C438S393000, C438S926000, C438S975000
Reexamination Certificate
active
06461941
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor device and, more particularly, to a method for the fabrication of a semiconductor device which is capable of preventing the occurrence of a defective die and misalignment otherwise induced by excessively polishing the edges of a wafer.
DESCRIPTION OF THE PRIOR ART
In fabrication processes of semiconductor devices with high-integration density such as 256M synchronous DRAM, an increased number of chemical-mechanical polishing (CMP) processes are applied. That is, a first CMP process involves polishing a high-density plasma oxide (HDP) in the formation of shallow trench isolation (STI) for providing electrical isolation between elements. A second CMP process involves polishing an interlayer insulating film covering a gate electrode. A third CMP process involves polishing a plug polysilicon film connected to the gate electrode via a contact hall formed within the interlayer insulating film. A fourth CMP process involves polishing an interlayer insulating film covering a bitline. A fifth CMP process involves subjecting an interlayer insulating film covering a capacitor to planarization.
Since an edge portion of the wafer has a lower pattern concentration relative to a central portion thereof, the edge portion may be subjected to an excessive CMP process.
There is shown in
FIG. 1
a layout of a die and alignment key on the wafer in the conventional fabrication process of a semiconductor device. As shown in
FIG. 1
, when an interlayer insulating film (not shown), which covers the wafer W obtained after forming a capacitor, is polished by the CMP process, a considerable difference in polishing level between the central portion and the edge portion of the wafer may be invoked, wherein a pattern including the capacitor is concentrated at the central portion of the wafer.
Accordingly, since a pattern collapse or a bridge may occur during a subsequent masking process, a die D
1
positioned at the edge of the wafer may not be employed as a final net die. The result is a decreased number of net dies on the wafer W. That is, the number of net dies during the formation of the capacitor is 148, but the number is decreased to 128 due to the unreasonable CMP process. As mentioned above, the conventional method suffers from a drawback in that the application of the excessive CMP process to the wafer edge allows the die D
1
positioned at the edge portion of the wafer to be damaged, causing a “dishing”, namely a dish-like depression on the surface of a pre-alignment key (PAK) and a global alignment key (GAK), which, in turn, makes alignment in a subsequent metal pattern process difficult.
SUMMARY OF THE INVENTION
It is, therefore, a primary object of the present invention to provide a method for the fabrication of a semiconductor device which is capable of preventing a defective die and an erroneous alignment which might otherwise be induced by a difference in polishing level between an edge and a central portion of a wafer.
In accordance with one aspect of the present invention, there is provided a method for the fabrication of a semiconductor device having a cell region on which a capacitor is formed, comprising steps of forming a group of dummy patterns around an alignment key of edges of a wafer, wherein the wafer is obtained by forming the capacitor on the cell region, and the dummy pattern has the same elevation as the capacitor formed on the cell region; disposing an interlayer insulating film on a resulting structure obtained after the forming step; and performing a chemical-mechanical polishing on the interlayer insulating film.
In accordance with another aspect of the present invention, there is provided a method for the fabrication of a semiconductor device having a cell region on which a capacitor is formed, comprising steps of forming a group of dummy patterns around an alignment key of edges of a wafer, while forming the capacitor on the cell region, wherein the dummy patterns have the same elevation as the capacitor formed on the cell region; disposing an interlayer insulating film on a resulting structure obtained after the forming step; and performing a chemical-mechanical polishing on the interlayer insulating film.
According to the present invention, a group of dummy patterns is formed around a die and alignment key of edges of a wafer in a bar shape, to thereby decrease a difference in pattern concentration between a central and an edge portion of the wafer. Furthermore, the present invention decentralizes a pad pressure using the dummy pattern during polishing processes to allow the pad pressure to be applied to the dummy pattern, thereby preventing an excessive CMP from being applied to dies placed adjacent to the edge of the wafer and preventing a dishing of the alignment key, resulting in an increased net die, improved accuracy and reduced misalignment.
REFERENCES:
patent: 6087733 (2000-07-01), Maxim et al.
patent: 6261918 (2001-07-01), So
patent: 6335560 (2002-01-01), Takeuchi
patent: 6373544 (2002-04-01), Hirabayashi
patent: 2001/0039086 (2001-11-01), Sato
patent: 2000208392 (2000-07-01), None
Hyundai Electronics Industries Co,. Ltd.
Jacobson & Holman PLLC
Lytle Craig P.
Smith Matthew
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