Memory device having memory cells with magnetic tunnel...

Details Memory device having memory cells with magnetic tunnel... Memory device having memory cells with magnetic tunnel...

2001-10-24

2002-10-29

Nelms, David (Department: 2818)

Static information storage and retrieval

Systems using particular element

Magnetic thin film

C365S158000, C365S171000

Reexamination Certificate

active

06473337

ABSTRACT:

TECHNICAL FIELD
The technical field is memory devices for storing data. More particularly, the technical field is memory devices having memory cells with tunnel junctions in series.
BACKGROUND
Memory devices are utilized in consumer electronic products to store data such as instructions utilized by the products. Nonvolatile memory devices are desirable because they do not require power to retain data. Therefore, data stored in nonvolatile memory devices is preserved when a power supply is exhausted or disconnected from the memory device. Consumers also prefer products of small volume and low cost, and the requirements of non-volatility, high density, and low cost are primary driving factors in the design of memory devices. Low power consumption is also desirable because smaller power sources can be used, reducing the size of consumer electronic products.
Nonvolatile memory devices typically have one time programmable (OTP) or re-programmable memory cells. A re-programmable memory cell can be switched among binary states. An OTP memory cell's state is permanent once the cell is programmed. OTP memory devices can generally be classified as one of fuse, anti-fuse, charge storage, or mask read only memory (mask ROM).
A fuse memory cell is programmed by applying a voltage across the cell so that the cell is “blown” during programming. The binary state of fuse memory cells can be detected as the resistance of the cell measured during a read process. Conventional fuse memory devices have a low array density because the contact regions required for each fuse element occupy a large area of the substrate. Conventional fuse memory cells also often include an isolation element such as a diode or transistor, which further increases cell size. Isolation diodes and transistors have limited current capability, and may be damaged by the write currents required to program the fuse memory cells. In addition, the isolation diodes and transistors are typically active silicon-based elements, which are most readily formed on a silicon crystal substrate. Isolation elements of this type may preclude stacking of multiple layers of fuse OTP arrays, decreasing possible device capacity. Silicon-based isolation elements such as micro-crystalline and amorphous diodes and transistors may enable stacking, but increase complexity and cost of fabrication.
Conventional anti-fuse memory cells typically include a metal-dielectric-metal stack. Conventional anti-fuse memory cells are programmed by applying a write potential across the cells. The write potential triggers the anti-fuse and reduces the resistance of a programmed memory cell. Conventional anti-fuse memory cells suffer many of the same disadvantages as fuse/transistor cells. For example, conventional anti-fuse memory cells may require silicon-based isolation elements, which decrease array density.
A common conventional charge storage memory is EPROM. EPROM memory utilizes Fowler-Nordheim tunneling to transfer charge from a substrate to a floating gate in the memory cell. EPROM memories require a large write voltage, and the write speed in EPROM devices is limited by tunneling current density.
Mask ROM memories are programmed at the time of fabrication, rather than at the user level (“field programming”). Therefore, each batch of mask ROM devices is application-specific. As in most manufacturing processes, cost savings are realized with increased volume. Therefore, in order for mask ROM production to be cost-effective, there must be a large demand for a particular application-specific memory. The requirement for large-scale processing renders mask ROM too costly for many applications.
A need therefore exists for a low-cost memory device having memory cells capable of high density arrangement. A need also exists for a memory device that does not require excessive processing power.
SUMMARY
According to a first aspect, a memory device includes dual tunnel junction memory cells having a magnetic tunnel junction in series with a tunnel junction. The magnetic tunnel junction can be changed from a first resistance state to a second resistance state during a write operation. The magnetic tunnel junction has a differing resistance-voltage characteristic than the tunnel junction, and the differing resistance-voltage characteristics allow the magnetic tunnel junction to be blown without blowing the tunnel junction during a write operation. The magnetic tunnel junction can function as an anti-fuse so that blowing the magnetic tunnel junction creates a short across the magnetic tunnel junction. The resulting change in resistance of the memory cell is detectable during a read operation.
According to the first aspect, the tunnel junction can provide an isolation function for the programmed memory cell when the magnetic tunnel junction is blown. Therefore, silicon-based isolation diodes and/or transistors are not required to isolate the memory cells in the memory device. The memory device can therefore include stacked layers of memory elements, increasing device capacity.
Also according to the first aspect, the memory cells are smaller than conventional memory cells having diode/transistor isolation elements. This aspect increases array density. The absence of diode/transistor isolation elements also simplifies the manufacture of the memory device.
According to a second aspect, a selected memory cell can be programmed by applying a write current or a write voltage to the memory cell. The resistance of the magnetic tunnel junction decreases more gradually than the tunnel junction when the write current or write voltage is applied.
According to the second aspect, a higher voltage is developed across the magnetic tunnel junction because of a higher resistance of the magnetic tunnel junction. As the resistance of the tunnel junction decreases more rapidly than the resistance of the magnetic tunnel junction, a greater portion of the voltage developed across the memory cell is across the magnetic tunnel junction. The write voltage or current can accordingly be selected so that the relatively high voltage across the magnetic tunnel junction exceeds a breakdown voltage of the magnetic tunnel junction, while the relatively low voltage developed across the tunnel junction does not exceed a breakdown voltage of the tunnel junction.
According to a third aspect, the breakdown voltages and resistance-voltage characteristics of the tunnel junction and the magnetic tunnel junction can be determined according to the materials used to form the magnetic tunnel junction and the tunnel junction.
According to the third aspect, manufacture of the memory cells is simplified because of the relative ease involved in varying the particular materials used to form the tunnel junctions.
According to a fourth aspect, the memory cells can be made using conventional processes, such as deposition and sputtering processes.
According to the fourth aspect, the memory device can be manufactured at relatively low cost.
Other aspects and advantages will become apparent from the following detailed description, taken in conjunction with the accompanying drawings.


REFERENCES:
patent: 5701222 (1997-12-01), Gill et al.
patent: 5991193 (1999-11-01), Gallagher et al.
patent: 6104632 (2000-08-01), Nishimura
patent: 6269018 (2001-07-01), Monsma et al.
patent: 6331944 (2001-12-01), Monsma et al.

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