Semiconductor memory device of low power consumption

Details Semiconductor memory device of low power consumption Semiconductor memory device of low power consumption

2001-07-25

2002-08-13

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S203000, C365S189110

Reexamination Certificate

active

06434065

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and in particular, to a configuration for reducing the current consumption in a standby state. The invention relates, more particularly, to a configuration for detecting, down to a minute current level, a leak current caused by a micro short circuit between a word line (row line) and a bit line, or the like, (column line) so as to repair this micro current path.
2. Description of the Background Art
FIG. 22
is a diagram schematically showing the configuration of an array part of a conventional semiconductor memory device. In
FIG. 22
, the configuration of a part related to bit lines of a dynamic random access memory (DRAM) requiring a refreshing operation that data is periodically restored.
In
FIG. 22
, memory cells MC are arranged in rows and columns. Corresponding to respective columns of the memory cells MC, bit line (column line) pairs BL
0
, /BL
0
to BLn, /BLn are arranged. These bit line pairs BL
0
, /BL
0
to BLn, /BLn are provided with bit line related circuits BK
0
to BKn, respectively, and the configuration of the bit line related circuit BK
0
corresponding to the bit line pair BL
0
and /BL
0
is specifically shown in FIG.
21
.
The bit line related circuit BK
0
includes a memory cell MCa provided corresponding to a crossing between the bit line BL
0
and the word line WL
0
, a memory cell MCb arranged corresponding to a crossing between the bit line /BL
0
and the word line WL
1
, a bit line isolation gate
3
responsive to a bit line isolation instructing signal BIL for isolating the bit lines BL
0
and /BL
0
from common bit lines CBL
0
and /CBL
0
, a sense amplifier
2
responsive to activation of sense amplifier driving signals SP and SN,for amplifying the difference of voltages between the common bit lines CBL
0
and /CBL
0
and a bit line precharging/equalizing circuit
1
activated upon activation of a bit line precharging/equalizing instructing signal BLEQ for precharging and equalizing the bit lines BL
0
and /BL
0
to a predetermined precharge voltage PBL
0
level via the common bit lines CBL
0
and /CBL
0
.
The same configuration is provided in the remaining bit line related circuits BKm to BKn.
The memory cells arranged in alignment in one row are connected to each of the word lines WL
0
and WL
1
.
The bit line isolation instructing signal BIL is applied in common to bit line isolation gates
3
included in these bit line related circuits BK
0
to BKn. In the same manner, the sense amplifier driving signals SP and SN are applied in common to sense amplifiers
2
included in these bit line related circuits BK
0
to BKn.
The bit line precharging/equalizing instructing signal BLEQ is applied in common to the bit line precharging/equalizing circuits
1
included in these bit line related circuits BK
0
to BKn. The bit line precharging/equalizing circuits
1
are divided into a plurality of groups. In
FIG. 22
, the bit line precharging/equalizing circuits
1
included in the bit line related circuits BK
0
to BKm, form one group and the bit line precharging/equalizing circuits
1
included in the bit line related circuits BKm+1 to BKn form another group.
The bit line precharging/equalizing circuits
1
included in the bit line related circuits BK
0
to BKm are connected to a local intermediate voltage transmission line
6
a
, and the bit line precharging/equalizing circuits included in the bit line related circuits BKm+1 to BKn are connected to a local intermediate voltage transmission line
6
b
. The local intermediate voltage transmission lines
6
a
and
6
b
are linked to the main intermediate voltage transmission line
5
via fusible link elements (fuse elements)
4
a
and
4
b
, respectively.
The memory cells MCa and MCb each include a capacitor QS for storing information and an access transistor (N channel MOS transistor) MT responsive to a signal potential on the corresponding word line WL (WL
0
, WL
1
) for connecting the capacitor QS to the corresponding bit line BL (BL
0
, /BL
0
).
The bit line isolation gates
3
each include a pair of transfer gates responsive to the bit line isolation instructing signals BIL for connecting the bit lines BL
0
and /BL
0
to the common bit lines CBL
0
and /CBL
0
, respectively. These bit line isolation gates
3
are provided because this DRAM has a shared sense amplifier configuration so that the sense amplifier
2
is shared between the adjacent bit line pairs, which are not shown. Upon reading out of data of the memory cells, the memory array, which includes a selected memory cell, is connected to the sense amplifiers
2
, while the non-selected memory array (memory array where no selected memory cells is present) is isolated from the corresponding sense amplifiers
2
by means of the corresponding bit line isolation gate.
The sense amplifier
2
includes a P sense amplifier responsive to activation of the sense amplifier driving signal SP for driving a common bit line of higher potential out of the common bit lines CBL
0
and /CBL
0
to the H level (logical high level) and an N sense amplifier for driving a common bit line of lower potential out of the common bit lines CBL
0
and /CBL
0
to the L level upon activation of the sense amplifier driving signal SN.
The P sense amplifier includes P channel MOS transistors P
1
and P
2
, having their gates and drains cross-coupled, while the N sense amplifier includes N channel MOS transistors N
1
and N
2
having their gates and drains cross-coupled. The sense amplifier driving signal SP is applied to the sources of these P channel MOS transistors P
1
and P
2
, while the sense amplifier driving signal SN is applied to the sources of the N channel MOS transistors N
1
and N
2
.
The bit line precharging/equalizing circuit
1
includes N channel MOS transistors N
3
to N
5
responsive to activation of the bit line precharging/equalizing signal BLEQ to become conductive. When rendered conductive, the N channel MOS transistor N
3
electrically short circuits the common bit lines CBL
0
and /CBL
0
. When rendered conductive, the N channel MOS transistors N
4
and N
5
transmit the intermediate voltage VBL, which is transmitted onto the local intermediate voltage transmission line
6
a
to the common bit lines CBL
0
and /CBL
0
, respectively. This intermediate voltage VBL is normally a voltage level of ½ times the voltages corresponding to the H level and to the L level of the data stored in memory cells.
In the standby state, the bit line isolation instruction signal BIL is at the H level (normally a voltage level higher than the power supply voltage) and the bit line isolation gates
3
in the bit line related circuits BK
0
to BKn are all in the conductive state. In the standby state, the bit line precharging/equalizing instruction signal BLEQ is also at the H level and the MOS transistors N
3
to N
5
in the bit line precharging/equalizing circuits
1
are all in the ON state, and the bit lines BL
0
, /BL
0
to BLn /BLn are all precharged and equalized to the intermediate voltage VBL level. The word lines WL
0
and WL
1
are in the non-selected state at the L level, and the access transistors in the memory cells MCa and MCb are in the non-conductive state.
In the memory cell selection operation, first, the bit line precharging/equalizing instruction signal BLEQ becomes the L level, and in the bit line related circuits BK
0
to BKn, the bit line precharging/equalizing circuits
1
transition into the non-activate state, and the bit lines BL
0
, /BL
0
to BLn, /BLn transition into the floating state at this intermediate voltage VBL level.
Then, an addressed row is driven to the selected state and data of the memory cells connected to this selected word line are transmitted to the corresponding bit lines. In the case where the word line WL
0
is selected, the voltage level of this word line WL
0
attains the H level and the access transistor MT in the memory cell MCa transitions into the ON state so that the charge held by the

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