Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-05-11
2002-02-12
Zarabian, Amir (Department: 2824)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C438S300000
Reexamination Certificate
active
06346732
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 11-134401, filed May 14, 1999; and No. 11-375404, filed Dec. 28, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device incorporating a semiconductor epitaxial substrate and a method of manufacturing the same. More particular, the present invention relates to a semiconductor epitaxial substrate incorporating an epitaxial layer formed on a semiconductor substrate through mediation of a native oxide film and a method of manufacturing the same. More particular, the present invention relates to a method of manufacturing a semiconductor device incorporating a MOS transistor formed by using an elevated source/drain technology for forming an epitaxial layer on a source/drain impurity diffused region by using selective epitaxial growth formed through mediation of a native oxide film, and a semiconductor device incorporating a SALICIDE (Self-Aligned Silicide) MOS transistor formed by using the manufacturing method.
Since devices for constituting an LSI have been shrinked, problems have been increased which exert influences on the performance of the LSI. The problems are exemplified by a short-channel effect of a MOS transistor element and increase of the parasitic capacitance. To solve the problems, a SOI (Silicon on Insulator) structure has been investigated.
The SOI structure encounters a problem in that the crystallinity of a channel region cannot easily be maintained. Therefore, at least a wafer bonding technology or SIMOX (Separation by Implanted Oxygen) technology must be used. The foregoing technologies cause the cost increase of material and decrease of manufacturing yield to occur. The foregoing technologies encounter considerably increase of the cost as compared with the conventional technology which uses CZ (Czochralski) substrate.
To obtain high electron mobility in the channel region, an attempt has been made such that a SiGe mixed crystal layer is formed on a silicon substrate so as to be used as the channel region. In the foregoing case, a silicon substrate must be used as the substrate because substrates having high quality are easily available.
To obtain high electron mobility, it is preferable that the mixing ratio of Ge is raised. Since the lattice constant of Si and that of Ge are different from each other, a high-quality epitaxial substrate free from the defects cannot be obtained when the Ge mixing ratio is 20% or higher.
To expand the range of the possibilities of the LSI structure, an attempt has been made such that a silicon epitaxial growth step is inserted into a process for manufacturing the semiconductor device. For example, a semiconductor device is formed, and then the silicon epitaxial growth is performed on the device. Thus, formation of the device is again performed so that multi-layered semiconductor device formation is permitted. As a result, the device formation density can considerably be raised.
To achieve the foregoing technology, a defect free silicon epitaxial layer must be formed. Therefore, it has been considered very important to sufficiently remove a native oxide film on the silicon substrate which obstructs the growth process before the silicon epitaxial growth is performed.
If impurities, such as oxygen, are present on the substrate even in a small quantity, defects, such as dislocations, generate in the silicon epitaxial layer starting with surface oxide. To remove surface oxide, a deoxidizing heat treatment must be performed in a high temperature region near 1000° C. Therefore, the formation process of the high-quality silicon epitaxial layer cannot easily be employed in the device employed, silicidation occurs between metal and the silicon substrate. Thus, deposited metal reacts with the silicon substrate, causing silicidation proceeds while the surface layer of the silicon substrate is being eroded.
Therefore, formation of the shallow SID region in the silicon substrate and formation of a shallow junction free from large leakage current between the silicon substrate and the SID region have been very difficult.
To solve the above-mentioned problem, employment of a method has been considered with which silicon single crystal is epitaxially grown on the SID region formed on the silicon substrate. Then, the SID region of the MOS transistor is elevated to be higher than the surface of the silicon substrate, and then metal is deposited. Then, silicidation is allowed to proceed.
The foregoing method is able to simultaneously meet both of the requirement for forming a low-resistance SID region required to maintain the high-speed operation of the MOS transistor and the requirement for forming a shallow junction in the lower portion of the surface of the silicon substrate. The structure of the MOS transistor formed by epitaxially growing silicon on the SID region formed on the silicon substrate is called an elevated SID structure.
Usually, the elevated SID structure is formed by manufacturing process, the processing temperature of which has an upper limit.
Since the operation speed of the MOS transistor has been raised and the structure of the same has been shrinked, a shallow source/drain impurity diffusion region (hereinafter called a SID region) of the MOS transistor has been required which has low resistance.
A high-performance transistor must have shallow junctions in the SID region. When a silicon layer is epitaxially grown on the SID region and implanting impurity ions upon the silicon epitaxial layer, shallow junctions can be formed from the surface of the silicon substrate. As described above, employment of the silicon epitaxial growth in the process for manufacturing the MOS LSI has become important in recent years.
In the conventional MOS LSI industrial field, there is a technology called a self-aligned silicide or SALICIDE for realizing a shrinked device which is capable of performing a high-speed operation. That is, metal, such as Co or Ti, is deposited in an impurity diffused region in a self-aligned manner to form silicide.
On the other hand, progress of the technology for shrinking semiconductor device raises a necessity for shallow SID diffused region in order to prevent the short channel effect. When the SALICIDE technology is performing heat treatment at 800° C. or higher by operating a LPCVD (Low Pressure Chemical Vapor Deposition) reactor. Therefore, the impurity profiles in the S/D region and the channel region, which has been formed by ion implantation, are changed. Thus, the designed performance cannot be exhibited.
Since B (boron) in the gate electrode is diffused into the channel region, the gate electrode is depleted, a critical problem arises in that the threshold voltage is changed.
To perform selective epitaxial growth, an UHVCVD (Ultra High Vacuum Chemical Vapor Deposition) reactor or the LPCVD reactor is usually used. In particular, it is preferable that the LPCVD reactor is used because the LPCVD reactor has frequently been employed in the ULSI manufacturing process and has an excellent track record from viewpoints of improving the manufacturing efficiency and the stability of the process.
A representative selective epitaxial growth using the LPCVD method is performed by a vapor phase epitaxial growth in a mixed atmosphere of a silicon source material, such as silane or dichlorosilane and etching gas of chlorine or hydrochloric acid.
Since thermal diffusion of dopants is tightly limited in the future shrinked semiconductor device, it is preferable that the thermal process of the CVD is performed at lower temperatures.
To obtain a practically satisfactory deposited film thickness by the vapor phase growth method using the LPCVD, high temperature heat treatment at 800° C. or higher is required. In the next generation device that has the gate length of 0.1 &mgr;m or shorter, change in the channel profile and diffusion of impurities from the gate to the channel ca
Kambayashi Shigeru
Mitani Yuichiro
Miyano Kiyotaka
Mizushima Ichiro
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
Wilson Christian D.
Zarabian Amir
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