Semiconductor device manufacturing: process – Making device array and selectively interconnecting – Using structure alterable to conductive state
Reexamination Certificate
2002-02-19
2002-10-01
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
Using structure alterable to conductive state
C438S467000
Reexamination Certificate
active
06458631
ABSTRACT:
The present invention relates to a method for fabricating an integrated circuit, in particular an antifuse, as known from U.S. Pat No. 6,087,677 and U.S. Pat. No. 5,904,507.
Although it can in principle be applied to any desired integrated circuits, the present invention and the problems on which it is based are explained in connection with integrated circuits fabricated using silicon technology.
FIGS. 2
a-d
diagrammatically depict various process steps involved in a known method for fabricating an integrated circuit using silicon technology.
In
FIG. 2
a
, reference numeral
1
denotes a circuit substrate made from silicon dioxide, into which two metallization regions
10
a
,
10
b
of tungsten have been introduced. This introduction of the metallization regions
10
a
,
10
b
can be achieved, for example, by, following a trench etching step, depositing tungsten over the entire surface of the circuit substrate
1
and then removing the tungsten by chemical mechanical polishing, in such a manner that the separate metallization regions
10
a
,
10
b
are formed.
The intention of the method shown is to allow, in addition to standard tungsten contacts on the first metallization region
10
a
, a second type of contact also to be created, in which a functional layer
15
rests on top of the second metallization region, with which contact is made from above by a contact. In the present case, the functional layer serves as a fusible link and consists cf SiN/Wsi
x
. However, it could also be a metallic barrier layer or the like.
As shown in
FIG. 2
b
, in a subsequent process step the functional layer
15
of SiN/Wsi
x
is deposited above the resulting structure, so that it covers the first and second metallization regions
10
a
,
10
b
. In a subsequent process step, a photomask
20
is formed in such a manner that it covers the functional layer
15
over the second metallization region
10
b
but leaves the functional layer
15
above the first metallization region
10
a
clear.
Then, referring now to
FIG. 2
c
, an etching process and a resist-stripping operation takes place, for example in an NF
3
-containing plasma, in order to remove the functional layer
15
above the first metallization region
10
a
. During this etching operation and during the stripping of the resist, an oxide film
100
comprising WO
x
is formed above the tungsten of the first metallization region
10
a
. A disadvantage is that it is impossible to avoid the formation of a WO
x
layer of this type.
As shown in
FIG. 2
d
, following the preceding process step, an insulating layer
25
, for example of silicon dioxide, is deposited over the entire surface of the resulting structure. Then, contact hole
12
a
,
12
b
are formed above the first and second metallization regions
10
a
,
10
b
, respectively, and these holes are filled with contacts
11
a
,
11
b
consisting of tungsten. This filling with the contacts can be effected in a similar manner to the formation of the first and second metallization regions
10
a
,
10
b
by depositing tungsten over the entire surface of the structure including the contact holes
12
a
,
12
b
and then partially removing this tungsten again by chemical mechanical polishing.
As can be seen from
FIG. 2
d
, in the known process the oxide film
100
is retained, and consequently the contact resistance between contact
11
a
and the first metallization region
10
a
is increased undesirably.
The general problem on which the present invention is based is therefore that the surfaces of certain metal layers or tracks, for example when tungsten is used as a metal, may oxidise at the surface under the action of certain etching gases.
By way of example, WO
x
layers of this type have the drawback of having a considerably higher resistance than pure tungsten, with the result that the contact resistance is increased with respect to higher levels which are connected thereto by a contact. Furthermore, some of the tungsten is consumed during the formation of the WO
x
tungsten layers, with the result that the sheet resistance of the tungsten track is increased and the planarity is disrupted.
FIG. 3
shows an example of a fusible link, in which a functional layer
30
of amorphous silicon is deposited above the level of the contact hole
12
comprising the contact
11
and is patterned, as is known, for example, from U.S. Pat. No. 6,097,077. After the patterning, an interconnect
40
is provided above the resulting structure, which the fusible link can be blown. The fact that the layer
30
of amorphous silicon has a considerable thickness and therefore requires high voltages and currents in order to be blown, has proven to be a drawback of this structure.
Therefore, it is an object of the present invention to provide a method for fabricating an integrated circuit in which it is possible to counteract deterioration of the contacts and an increase in the bulk resistance as a result of the etching of the functional layer and tie stripping of the resist and, at the same time, thin functional layers are possible.
According to the invention, this object is achieved by the fabrication method described in Claim 1.
The idea on which the present invention is based consists in placing the functional layer or fuse layer in an opening which is situated in a further insulating layer on the contact insulating layer. As a result, the metallization level is protected during patterning of the functional layer.
Compared to the known attempted solution, the fabrication method according to the invention has the advantage, inter alia, that a thin fuse or the like is obtained, the patterning of which does not attack the metallization below it.
The subclaims define advantageous refinements and improvements of the fabrication method given in Claim 1.
According to a preferred refinement, the functional layer is formed by depositing a layer stack having at least two layers, the lower layer being a further insulating layer and the upper layer being a conductive layer.
According to a further preferred refinement, a further metallization region is formed in the circuit substrate in the plane of the first metallization region, and a further contact is formed, at the same time as the first contact, in the first insulating layer, outside the opening, in order to make contact with the further metallization region.
According to a further preferred refinement, the lower layer contains Si
3
N
4
, SiO
2
or combinations thereof.
According to a further preferred refinement, the upper layer comprises a metal, a metal compound or polysilicon.
According to a further preferred refinement, the lower layer is an Si
3
N
4
layer which is from 1 nm to 5 nm thick, and the upper layer is a WSi layer which is from 0 to 30 nm thick.
REFERENCES:
patent: 5904507 (1999-05-01), Thomas
patent: 6081021 (2000-06-01), Gambino et al.
patent: 6087677 (2000-07-01), Wu
patent: 6097077 (2000-08-01), Gordon et al.
patent: 6124194 (2000-09-01), Shao et a.
patent: 6335228 (2002-01-01), Fuller et al.
Ayadi Kamel
Brintzinger Axel
Dankowski Stefan
Frey Ulrich
Lehr Matthias
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