Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
2001-01-09
2002-10-08
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
With measuring or testing
C438S015000, C438S016000, C438S017000
Reexamination Certificate
active
06461879
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor device testing, and more particularly, to testing of semiconductor devices of a wafer.
2. Discussion of the Related Art
In the processing of semiconductor devices, after the formation of a number of integrated circuit devices on a silicon wafer, and prior to sawing the wafer into individual die, each integrated circuit device undergoes a succession of electrical tests including, for example, tests for open circuits, shorts, device logic functions, and device speed. This is typically undertaken (
FIG. 1
) by positioning the wafer
16
on a vacuum chuck
10
, vacuum being applied to passages
12
on the substantially flat surface
14
of the chuck
10
and holding the wafer
16
onto the surface
14
of the chuck
10
, so that the wafer
16
is also held in a substantially flat, i.e., physically unstressed state. Then, individual integrated circuit devices of the wafer
16
are contacted by electrical probes
18
and the tests specified above are undertaken on each of the integrated circuit devices in succession. Those integrated circuit devices that do not successfully pass the tests are marked, and, after sawing the wafer
16
into individual die, are discarded. The remaining die, having passed the electrical tests, go through the steps of die attach, wire bond, encapsulation, final electrical test, mark and pack.
During the die attach step, individual die
20
are secured to a copper lead frame
22
by means of epoxy
24
, for example, silver-filled epoxy
24
(FIG.
2
). In this process, the die-epoxy-lead frame combination is heated to a temperature of, for example, 175° C. for a period of, for example 30 minutes, to cure the epoxy
24
, and then the structure is allowed to cool. During this cooling process, the silicon die
20
, with a low coefficient of thermal expansion, shrinks a very small amount, while the copper
22
, with a high coefficient of thermal expansion, shrinks a substantial amount. This results in the top surface of the die
20
being stretched so as to be physically stressed radially toward its center, as shown in
FIG. 3
(see arrows). This change in the die
20
from an unstressed to a stressed state can result in significant changes in the electrical characteristics of the die
20
, as compared to those revealed by the testing of the die
20
as part of the wafer
16
, in an unstressed state. These differences in electrical characteristics will only be revealed upon final electrical test, that is, after the long and expensive series of operations including saw, die attach, wire bond and encapsulation.
If the changes in electrical characteristics due to changes in the stressing of the die
20
could to some degree be known prior to the sawing of the wafer
16
into individual die
20
, it could with some certainty be predicted which integrated circuit devices, while passing the electrical tests at the wafer level, would be perturbed or fail at the packaged level, so that the expensive steps of saw, die attach, wire bond and encapsulation would not be undertaken on those die. In addition, if the changes in electrical characteristics due to changes in the stressing of the die could be known, such changes could be compensated for in the initial design of the integrated circuit device, resulting in a higher number of packaged devices passing final electrical testing.
Therefore, what is needed is a process that allows prediction of the performance of an electrical device after packaging thereof based on testing of the die at the wafer level, and a tool for use in such process. Furthermore, the process should be simple and effective, and the tool itself should also be simple and convenient in use in furtherance of practicing the process.
SUMMARY OF THE INVENTION
The present process is a method for testing one or more die as part of a semiconductor wafer, comprising electrically testing a die of a wafer in an unstressed state, physically stressing the die of the wafer to a first stressed state, electrically testing the die in its first stressed state, physically stressing the die of the wafer to a second stressed state, electrically testing the die in its second stressed state, and comparing the electrical test results of these steps. The tool for undertaking this process has a tool body which includes an annular portion on which the wafer is supported, and a recessed portion into which vacuum is applied, to provide for bending of the wafer into the recessed portion to stress the die of the wafer.
The present invention is better understood upon consideration of the detailed description below, in conjunction with the accompanying drawings. As will become readily apparent to those skilled in the art from the following description, there is shown and described an embodiment of this invention simply by way of the illustration of the best mode to carry out the invention. As will be realized, the invention is capable of other embodiments and its several details are capable of modifications and various obvious aspects, all without departing from the scope of the invention. Accordingly, the drawings and detailed description will be regarded as illustrative in nature and not as restrictive.
REFERENCES:
patent: 4603867 (1986-08-01), Babb et al.
patent: 6147506 (2000-11-01), Ahmad
Blish II Richard C.
Sidharth
Advanced Micro Devices , Inc.
Berry Renee′ R.
Nelms David
Winters Paul J.
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