Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-12-14
2002-11-12
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C703S016000
Reexamination Certificate
active
06480988
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the electronic design of integrated circuits, and more specifically to a method and apparatus for the functional verification of a target integrated circuit design.
2. Related Art
Functional verification is one of the steps in the design of many integrated circuits. Functional verification generally refers to determining whether a design (“target design”) representing an integrated circuit performs a function it is designed for. In a typical design process, a designer identifies the functions to be performed and designs a circuit using high-level languages (e.g., VHDL language well known in the relevant arts) to perform the identified functions. An example of a function may be to generate a predetermined output data corresponding to a given input data. Tools available in the industry are typically used to generate a lower-level design (e.g., at gate-level) from the design specified in a high-level language. The higher level languages are generally more understandable to a user (human-being) while the lower level languages are closer in representation to the physical implementation.
Usually, the lower level design is evaluated against input data to generate output data. A determination of the accuracy of a functional design may be made based on the output data. The manner in which input data is generated and output data is used for determination of accuracy may depend on the specific type of verification environment. For example, in an emulation environment, the target design receives input data in a “real environment” usually having other components, whose operation can be relied on for accuracy. The target design is implemented to typically operate at least with these other components. By testing the target design in combination with these other components, functional verification of the target design can be performed. In general, a functional verification system operating in an emulation environment needs to generate output data values quickly such that the output data is available in a timely manner for the other components.
In contrast, in a simulation environment, a designer specifies pre-determined input data and evaluates the target design against the input data. The output data generated by the evaluation is examined to determine whether the design performs the desired functions. Once a designer is satisfied with a design, the data representing the design is sent for fabrication as an integrated circuit.
Accuracy in the functional verification is an important requirement in the design process for several reasons. For example, it is relatively less expensive to alter a circuit design prior to fabrication compared to re-designing and sending the design data for fabrication. In addition, it may require several weeks of time to redesign and complete fabrication again. Such levels of delays may be unacceptable, particularly in the high- technology markets where short design cycles are generally important.
In addition to accuracy, the verification step needs to scale well to the functional verification of integrated circuits of large sizes. That is, a verification systems needs to provide for verification of integrated circuit designs of large sizes. As is well known, an integrated circuit (semi-conductor chip) can include transistors of the order of a few millions, and the number has been increasing over time.
Furthermore, it is generally desirable that the verification step be completed quickly or with minimal internal computations. The speed of verification is particularly important in view of the increase in size and complexity of integrated circuits. To decrease the total design cycle time, it is desirable that the functional verification be completed quickly.
Co-pending U.S. patent application entitled, “Functional Verification of Integrated Circuit Designs”, Ser. No. 09/097,874, Filed: Jun. 15, 1998, describes some functional verification systems in which a target design is partitioned into many combinatorial logic blocks connected by sequential elements (e.g., flip-flops) and with appropriate dependencies. The state tables corresponding to the logic blocks are evaluated and stored in multiple random access storage devices (RASDs).
The output corresponding to each input combination is stored such that the output is retrieved from the corresponding RASD when the input combination is provided as a memory address to the RASD. For example, assuming a four input combinatorial logic and a RASD having four bits address bus, if the output the combinatorial logic is to be a 1 corresponding to an input of 1011, a ‘1’ is stored in the memory location corresponding to address 1011.
Cross-connects (XCONs) may interconnect the RASDs and enforce the dependencies which preserve the overall function of the target design. In general, the XCONs provide the outputs resulting from evaluation as memory addresses to RASDs. An XCON may be connected to multiple RASDs, and the XCON together with the connected RASDs may be referred to as a combinatorial logic output evaluator (CLOE).
In an approach described in the co-pending application noted above, each CLOE is connected to 16 other CLOEs (termed as neighbors). One of these CLOEs acts as a central CLOE to communicate with other groups of 16 CLOEs. In other words, if the output of a combinatorial logic evaluated in a first group and the output is to be provided as an input to a RASD in another group, the central CLOEs of the two groups may need to communicate to enable the necessary data transfer.
Such an approach may have several disadvantages. For example, the scheduling of evaluation of a combinatorial block may be undesirably complicated as the inputs may need to be communicated from several CLOEs and due to the ‘hierarchy’ in communication resulting from the central CLOE. Accordingly, the embodiments of the co-pending application may not be suitable in some environments.
Therefore, what is needed is a method and apparatus which enables the CLOE outputs to be communicated in an efficient manner such that the evaluations can be scheduled and performed quickly. In addition, the approach generally needs to allows for one or more of several related features such as tracing, verification of cycle based and non-cycle based designs, etc.
SUMMARY OF THE INVENTION
The present invention enables the functional verification of both cycle-based and non-cycle based designs. In an embodiment, evaluation units are designed to evaluate one of several combinatorial blocks within a cluster in response to receiving a cluster number identifying the corresponding cluster. The combinatorial blocks together specify a target design including data dependencies. A flow control memory stores flow control instructions indicating the sequence in which the clusters are to be evaluated. A flow processor sends a sequence of cluster numbers to the evaluation units to cause the target design to be evaluated.
To facilitate the evaluation of non-cycle based designs which contain loops, a register is used to store data indicating a condition under which the evaluation of a loop is to be terminated. A cluster control memory stores data indicating the manner in which the register is to be modified upon evaluation of the clusters. The flow control memory may store data indicating a sequence in which the cluster numbers are to be sent depending on different values in the register. As a result, loops of non-cycle based designs may be implemented in accordance with the present invention.
Further features and advantages of the invention, as well as the structure and operation of various embodiments of the invention, are described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number.
REFERENCES:
patent: 5625567 (1997-04-01), Mankin et al.
pa
Broukhis Leonid Alexander
Ganesan Subbu
Narayanaswamy Ramesh
Nixon Ian Michael
Kik Phallaka
Law Firm of Naren Thappeta
Smith Matthew
Tharas Systems Inc.
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