Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-03-29
2002-06-04
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C438S671000
Reexamination Certificate
active
06399992
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-090060, filed Mar. 29, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a method of making the same, particularly, to a semiconductor device having a high punch-through voltage and a method of making the same.
With progress in a fine pattern of the design rule of a semiconductor device, a well isolation punch-through voltage has come to attract attentions depending on a boundary pattern between a p-well and an n-well in the case where the boundary pattern between the p-well and the n-well is present under an STI (shallow trench isolation) region formed selectively in a semiconductor substrate.
It is significant to compare, for example, the case shown in
FIG. 7A
, in which a boundary pattern
74
between a p-well
71
and an n-well
72
is straight, with the case shown in
FIG. 7B
, in which a boundary pattern
75
between the p-well
71
and the n-well
72
has right-angled corners.
Where the boundary pattern
74
between the wells is straight as shown in
FIG. 7A
, a distance L between diffused regions
73
and the boundary pattern
74
is given by, for example, 0.15 &mgr;m, which is required for obtaining a desired punch-through voltage therebetween. In this case, the diffused region
73
is formed in the p- and n-wells and represents a drain or source region of MOS FETs, a contact region, an active area, etc.
On the other hand, where the boundary pattern
75
between the wells
71
and
72
has a right-angled corner
76
as shown in
FIG. 7B
, a depletion layer
78
extends from the corner
76
toward a corner portion
77
of the diffused region
73
formed in the p-well
71
as denoted by an arrow (vector). The magnitude of the depletion layer
78
is given as a synthesized vector of depletion layers
791
,
792
extending from the boundary pattern
75
in directions perpendicular to the boundary pattern
75
, as denoted by arrows (vectors). Therefore, in order to ensure a desired punch-through voltage, required is, for example, 0.35 to 0.4 &mgr;m of the distance L between the diffusion region
73
formed in the p-well
71
and the well boundary
75
. In other words, a remarkable difference is generated in the distance L as compared with the straight pattern. To be more specific, the distance L of 0.35 to 0.4 &mgr;m given above is 3 to 4 times as long as the distance L in the case where the boundary pattern
75
is straight.
In such a case, a design rule is set on the basis of the well isolation punch-through voltage in the corner of the boundary pattern of the well. In other words, the distance between the diffused region and the well boundary is set to 0.4 &mgr;m even in the case where the boundary pattern is straight. Alternatively, another moderated design rule is set for the corner of the boundary pattern of the well. However, the setting of such a design rule is disadvantageous in area and is obstructive to the fine device structure.
It should also be noted that, if the impurity concentration in the well is increased in an attempt to increase the well isolation punch-through voltage in the corner of the boundary pattern of the well, the junction capacitance of the well boundary is increased, which is disadvantageous in terms of the improvement of the operating speed of the element formed in the well.
On the other hand, the trench edge of the STI region requires a rounding control having a curvature in order to suppress the kink characteristic, as apparent from the cross sectional structure of the trench in the STI region shown in FIG.
8
. The conventional process of forming a trench and the conventional rounding control process of the trench edge will now be described.
In the first step, a SiO
2
film
81
is formed on a p-type Si substrate
80
, followed by forming a SiN film
82
on the SiO
2
film
81
and subsequently forming a SiO
2
film
83
on the SiN film
82
. Then, the SiO
2
film
83
, the SiN film
82
and the SiO
2
film
81
are selectively etched successively by a lithography technique and an anisotropic etching, e.g., RIE (reactive ion etching).
In the next step, the Si substrate
80
is etched in a depth of 0.5 &mgr;m by RIE, using the remaining SiO
2
film
83
, the SiN film
82
and the SiO
2
81
as a mask, thereby forming a trench
84
for the STI (shallow trench isolation) region.
After the RIE step for the trench formation, a SiO
2
film
87
is formed after removing a damaged layer on the substrate surface
86
within the trench
84
by Si dry etching caused by the RIE treatment, and carrying out a corner rounding oxidizing treatment for rounding the trench edge
85
.
Then, an insulating film, e.g., a SiO
2
film (not shown), is buried in the trench
84
to provide an STI region. Thereafter, an SiO
2
film is deposited over the entire surface of the substrate, followed by planarizing the SiO
2
film by a chemical mechanical polishing (CMP) method. The SiO
2
film is further etched with NH
4
F or a dry etching until the SiN film
82
is exposed to the outside, thereby leaving the remaining SiO
2
film buried in the trench
84
. Further, after the SiN film
82
is removed by etching, a heat treatment is applied for lowering the film stress of the buried SiO
2
film. Then, the ordinary processes of the well-channel forming steps is carried out.
In the conventional method described above, however, the isolation width of the finished element is increased, leading to a large difference between the design size defined by the mask size and the size after the processing. In order to obtain a desired design size, the difference in the processing size must be absorbed.
Under the circumstances, in the prior art, since the width of the source or drain region is exposed in the patterning step set smaller in so as to be smaller than the design size in anticipation of the amount of the difference in the processing size, the exposure margin for the fine isolation is reduced.
As described above, if the design rule is set in a manner to ensure a desired well isolation punch-through voltage in the case where the boundary pattern of the wells has the corner as shown in the conventional semiconductor device, the design rule thus set is obstructive to the fine device structure. Also, if the impurity concentration in the well is increased in an attempt to increase the well isolation punch-through voltage in the corner of the boundary pattern, the junction capacitance of the well boundary is increased, which is disadvantageous for the high speed operation of the element formed in the well.
Further, in the conventional processing method in which a corner rounding oxidation is performed for the rounding control of the trench edge of an STI region, the finished isolation width is increased, leading to a large difference between the design size defined by a mask size and the finished size.
BRIEF SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device having a desired well isolation punch-through voltage and adapted for a fine device structure.
Another object of the present invention is to provide a semiconductor device that permits suppressing the increase in the junction capacitance in the well boundary to allow the semiconductor device to be operated at a high speed.
Another object of the present invention is to provide a method of making a semiconductor device having the fine device structure while ensuring a desired well isolation punch-through voltage without reluxing the design rule.
According to one aspect of the present invention, there is provided a semiconductor device which comprises a semiconductor substrate; a first well, provided in the semiconductor substrate, having a first conductivity type; a second well adjacent to the first well, provided in the semiconductor substrate, having a second conductivity type opposite to the first conductivity type;
Igarashi Hirofumi
Matsumoto Masahiko
Pillsbury & Winthrop LLP
Vu David
LandOfFree
Semiconductor device and method of making the same does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device and method of making the same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device and method of making the same will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2958201