Integrated circuit asymmetric transistors

Details Integrated circuit asymmetric transistors Integrated circuit asymmetric transistors

2000-08-31

2002-11-19

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Introduction of conductivity modifying dopant into...

Ion implantation of dopant into semiconductor region

C438S525000, C438S174000, C438S179000, C438S183000, C438S217000, C438S286000, C438S289000, C257S336000, C257S244000, C257S402000, C257S403000, C257S408000

Reexamination Certificate

active

06482724

ABSTRACT:

FIELD OF THE INVENTION
The invention is generally related to the field of MOSFET transistors and more specifically to forming an asymmetric MOSFET structure using a disposable gate process.
BACKGROUND OF THE INVENTION
As CMOS technology continues to scale further into the sub-micron region, it becomes increasingly difficult to achieve a high transistor on current I
on
with a low transistor off current I
off
. One way to achieve this performance is to use an idealized MOS transistor structure. In such a structure, the channel of the MOS transistor has a high threshold voltage region and a low threshold voltage region. This can be achieved by preferential channel doping. Such a MOS transistor would have an asymmetric channel doping profile where the channel would be doped such that the threshold voltage VT at the drain side (i.e., adjacent to the drain region) would be low (eg. <0) whereas at the source side (i.e., adjacent to the source region) the threshold voltage would be high enough to suppress transistor Ioff when the transistor is biased off.
Using conventional MOSFET fabrication methods, asymmetric MOSFETs have been formed using angled pocket implants as shown in FIG.
1
and angled source drain implants as shown in
FIG. 2. A
asymmetric MOSFET transistor according to the prior art is shown in FIG.
1
. The transistor is formed in a silicon substrate
10
and comprises source/drain extensions
50
formed using the sidewall spacers
40
. The source/drain extensions
50
are self-aligned to the source and drain regions
60
of the MOSFET. A gate dielectric
20
separates the gate electrode
20
from the channel region in the substrate
10
. The film
25
is a dielectric film that is formed on the silicon substrate
10
but in not under the gate electrode. As shown in
FIG. 1
, an angled pocket implant
95
is performed to form the asymmetric regions
96
around the transistor source and drain regions
60
. This angled implant
95
can be performed before or after the sidewall
40
formation. As shown in
FIG. 2
, angled source drain implants
102
will result in asymmetric source and drain regions
62
which will form an asymmetric transistor. In either case, in order to alter the doping close to the silicon surface under the gate, the dopants are also placed deep into the substrate beneath the gate where they compromise transistor performance. In particular, it becomes difficult to achieve a very low threshold voltage on the drain side of the channel without simultaneously causing large short channel effects which are undesirable. In fabricating asymmetric transistors it is desirable to achieve low threshold voltage using a relatively abrupt lightly doped or compensated region near the channel surface beneath the gate of the transistor.
SUMMARY OF THE INVENTION
This invention is a method for fabricating an asymmetric transistor. In an embodiment of the instant invention, the method comprises: providing a silicon substrate with a region of a first conductivity type; forming an insulator layer over said substrate; forming a disposable gate over said insulator layer over said substrate region of said first conductivity type; forming a plurality of sidewall structures adjacent to said disposable gate; forming source and drain regions adjacent to said sidewall structures; forming an insulator layer over said source and drain regions; removing said disposable gate to form a gap between said plurality of sidewall structures without substantially removing any other exposed material; implanting a first dopant species of a first conductivity type into said gap to form a high threshold voltage region; removing said insulator layer in said gap exposing a portion of said silicon substrate; forming a gate dielectric over said exposed portion of said silicon substrate; and forming a gate electrode over said gate dielectric.
In another embodiment of the instant invention, the method comprises: providing a silicon substrate with a region of a first conductivity type; forming an insulator layer over said substrate; forming a disposable gate over said insulator layer over said substrate region of said first conductivity type; forming a plurality of sidewall structures adjacent to said disposable gate; forming source and drain regions adjacent to said sidewall structures; forming an insulator layer over said source and drain regions; removing said disposable gate to form a gap between said plurality of sidewall structures without substantially removing any other exposed material; implanting a second dopant species of a second conductivity type into said gap to form a low threshold voltage region; removing said insulator layer in said gap exposing a portion of said silicon substrate; forming a gate dielectric over said exposed portion of said silicon substrate; and forming a gate electrode over said gate dielectric.
In another embodiment, the method comprises: providing a silicon substrate with a region of a first conductivity type; forming an insulator layer over said substrate; forming a disposable gate over said insulator layer over said substrate region of said first conductivity type; forming a plurality of sidewall structures adjacent to said disposable gate; forming source and drain regions adjacent to said sidewall structures; forming an insulator layer over said source and drain regions; removing said disposable gate to form a gap between said plurality of sidewall structures without substantially removing any other exposed material; implanting a first dopant species of a first conductivity type into said gap to form a high threshold voltage region; implanting a second dopant species of a second conductivity type into said gap to form a low threshold voltage region; removing said insulator layer in said gap exposing a portion of said silicon substrate; forming a gate dielectric over said exposed portion of said silicon substrate; and forming a gate electrode over said gate dielectric.
One advantage of the above described method is the forming of an asymmetric transistor without a degradation in transistor performance. This and other technical advantages of the instant invention will be readily apparent to one skilled in the art from the following FIGUREs, description, and claims.


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