Semiconductor device manufacturing: process – Chemical etching – Liquid phase etching
Reexamination Certificate
2001-02-07
2002-12-03
Kunemund, Robert (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Liquid phase etching
C438S747000, C438S750000, C438S756000, C438S757000
Reexamination Certificate
active
06489251
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor etching method. More particularly, the present invention relates to the method of forming a slope lateral structure.
BACKGROUND OF THE INVENTION
A ROM is a nonvolatile memory device in which stored data are not changed in a normal operation state. A ROM is classified according to the methods for storing data into the ROM. There are a mask read only memory (MROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM) and an erasable and electrically programmable ROM (EEPROM).
The mask ROM is coded with its data, i.e., has the data stored in it, by using a specialized mask (representing particular required for a user) during the fabrication process. Data stored in a mask ROM is not able to be changed, rather it is only possible to read the data. A type of mask ROM causes a predetermined transistor has a status that differs from other transistors by implanting impurity ions, so that a datum is coded. That is, the mask ROM causes a predetermined transistor to have an OFF state by implanting impurity ions during fabrication. Transistors for which impurity ions are not implanted during fabrication have an ON state, and vice versa. Therefore, the data are coded.
As illustrated in
FIG. 1
, a conventional mask ROM has a buried oxide layer
19
which is perpendicular to a wordline of gate
23
. A high concentration buried diffusion region (buried diffusion region ) made of a common source and drain region and used for a bit line is formed under the buried oxide layer
19
, so that the word line is perpendicular to the bit line. Accordingly, the word line and the bit line intersect and form transistors. First and second transistor channels
27
and
29
are formed between the buried diffusion regions under the buried oxide layer
19
, overlapping with the gate
23
. The transistor T
1
having the first channel
27
that is coated with P conductivity type material maintains the OFF state, and the other transistor T
2
having the uncoated second channel
29
is not programmed and maintains the ON state.
As illustrated in
FIG. 2
, a gate oxide layer
17
and a buried oxide layer
19
are formed on a P type semiconductor substrate
11
. The buried oxide layer
19
is thicker than the gate oxide layer
17
. A buried diffusion region
21
having N type impurity ions is formed under the buried oxide layer
19
. The buried diffusion region
21
is the common source/drain of the transistors and used for a bit line. A gate
23
, perpendicular to the buried diffusion region
21
, is formed on the gate oxide layer
17
. A portion of the semiconductor substrate
11
, positioned opposite to the gate
23
becomes the first and second channels
27
and
29
. The transistor T
1
having the first channel
27
is made of the P type impurity ions and maintains the OFF state. The transistor T
2
having the second channel
29
maintains the ON state.
A process for forming the above-described conventional mask ROM will now be described with reference to
FIGS. 3A-3D
.
As illustrated in
FIG. 3A
, a first photosensitive layer
13
is deposited on the semiconductor substrate
11
made of P type silicon. The photosensitive layer
13
is exposed to light, developed and patterned to expose selected portions of the semiconductor substrate
11
. An N type impurity ion such as As or P is heavily doped in the semiconductor substrate
11
, using the first photosensitive layer
13
as a mask, to form an ion implanted region
15
.
As illustrated in
FIG. 3B
, the first photosensitive layer
13
is eliminated. The surface of the semiconductor substrate
11
is implanted with impurities during a thermal oxidation process, and the gate oxide layer
17
is formed on a portion where ions are not implanted. The rate of oxidation in the portion of the semiconductor substrate
11
where the ion implanted region
15
is formed is 1 to 2 times faster than that of the portion where ions are not implanted due to a lattice damage, enabling the formation of a thick buried oxide layer
19
. During thermal oxidation, impurity ions in the ion implanted region
15
are activated, so that their function as the common source and drain region. The buried diffusion region
21
is used for the bit line.
As illustrated in
FIG. 3C
, impurity ions such as polycrystal silicon or CoSi are doped on the gate oxide layer
17
and the buried oxide layer
19
using chemical vapor deposition (CVD). They are patterned to be perpendicular to the buried diffusion region
21
in a photolithography method, effectively forming a wordline gate
23
. Therefore, there is formed the transistor whose channel is the portion corresponding to the gate
23
between the buried diffusion regions
21
of the semiconductor substrate
11
. The second photosensitive layer
24
is deposited on the overall surface of the substrate, exposed to light, developed and patterned to expose the predetermined transistor. Impurity ions such as B or BF
2
are heavily implanted in the substrate to form the ion implanted region
25
, using the second photosensitive layer
24
as a mask.
As illustrated in
FIG. 3D
, the second photosensitive layer
24
is eliminated. The impurity ions in the ion implanted region
25
are heat-treated and diffused to form the first channel
27
, where P type impurity ions are heavily doped. The channel where the P type impurity ions are not doped becomes the second channel
29
. The transistor T
1
that is used for the first channel
27
is coded, and the other transistor T
2
that is used for the second channel
29
is not coded.
The process for forming the conventional mask ROM is described above. In order to efficiently protect the buried diffusion region
21
in the process of implanted B or BF
2
ion, a new process to prevent the coded failure, which is caused by the wider pattern of second photosensitive layer or error alignment is provided. A protective layer
35
is formed on the buried diffusion region
21
to replace the conventional buried oxide layer. As illustrated in FIG.
4
.
However, the protective layer
35
can protect the buried diffusion region
21
, but a big problem of forming the wordline gate
23
in the subsequence process is happened. The structure of the protective layer
35
has vertical laterals, so that the residue of polycrystal silicon or CoSi is formed on the vertical laterals after etching the wordline process. Due to the incomplete etching process, the wordlines are connected by the residue formed on the laterals of the protective layer, and the characters of the MROM are affected.
SUMMARY OF THE INVENTION
It is therefore an objective of this invention to provide a method of forming a slope lateral structure. In this invention, the silicon nitride and the silicon hydroxide with different etching rates are used. Thus, when the silicon nitride is etching, the top and laterals portions of the silicon hydroxide is suffering the slight etching. So that, when the silicon nitride is etched completely, a slope lateral silicon hydroxide is formed, because of the different etching time on the top and the bottom of the silicon hydroxide.
It is another objective of this invention to provide a method of forming a slope lateral structure. Using the present invention, the conventional NROM process problem, which the wordlines are connected by the residue on the laterals of the protective layer after etching process can be solved.
In accordance with the foregoing and other objects of this invention, this invention provides a method of forming a slope lateral structure during NROM fabrication process, comprising the steps of: providing a semiconductor substrate; forming a silicon nitride layer on the substrate, and then developing and patterning the silicon nitride layer to expose a plurality of selected portions of the semiconductor substrate; forming a silicon hydroxide layer overlaying the silicon nitride layer and the semiconductor substrate; polishing a surface of the silicon hydroxide layer to expose the silicon nitride layer and the silicon hydro
Kunemund Robert
Macronix International Co. Ltd.
Tran Binh X.
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