Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-03-26
2002-11-05
Niebling, John F. (Department: 2812)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S411000, C257S412000
Reexamination Certificate
active
06476454
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a method of manufacturing the same, particularly, to a transistor in which the gate electrode is formed by a damascene gate process, i.e., a burying method, and a method of manufacturing the same.
In recent years, a large scale integrated circuit (LSI) in which a large number of transistors, resistors, etc. are connected to form an electric circuit and are integrated on an single chip is used in an important portion of a computer or a communication equipment. Therefore, the performance of the entire equipment is deeply related to the performance of the LSI body. The performance of the LSI body can be improved by increasing the degree of integration, i.e., by miniaturizing the element. When it comes to, for example, a MOS field effect transistor (MOS transistor), the miniaturization of the element can be achieved by decreasing the gate length and by decreasing the thickness of the source-drain regions.
A low acceleration ion implantation method is widely employed as a method of forming shallow source-drain regions. Source-drain regions having a depth not larger than 0.1 &mgr;m can be formed by this method. However, the impurity diffusion layer formed by the low acceleration ion implantation method has a high sheet resistance of at least 100&OHgr;/cm
2
, making it difficult to achieve a high speed operation by the miniaturization. Such being the situation, a salicide is employed for decreasing the resistance of the source-drain-gate in a device requiring a high speed operation such as a LOGIC-LSI. The term “salicide” noted above denotes that a silicide film is formed by self-alignment on the surfaces of the source-drain diffusion layers and the gate electrode (n+ or p+ polycrystalline silicon).
In the case of employing a dual gate, in which an n+ polycrystalline silicon (polysilicon) and a p+ polysilicon are used as the underlying layers of the silicide layer within the same layer, the salicide structure permits not only decreasing the resistance of the gate electrode but also simplifying the process. The particular effect can be obtained because the employment of the salicide structure makes it possible to achieve doping of an impurity into the gate polysilicon in the step of an impurity doping in the source-drain regions. On the other hand, in the case of employing a W polycide as a gate electrode, it is necessary to perform at different timings the step of dividing the polysilicon in the bottom portion of the gate electrode into an n
+
doping and a p
+
doping and the step of dividing the source-drain into an n
+
doping and a p
+
doping. It follows that additional steps are required including two times of the lithography step, two times of the ion implantation step, and two times of the resist removing step.
On the other hand, SAC (self-aligned contact) is absolutely required in the device requiring the design of a high density element such as a memory LSI. In the SAC structure, the gate electrode surface must not be exposed to the outside in the step of forming a contact hole in an insulating film on the source or drain region. Therefore, it is necessary to form a silicon nitride layer, which acts as a stopper film in the step of subjecting a silicon oxide film to a reactive ion etching (RIE), on the gate electrode surface. It follows that, in the case of a memory LSI, it is impossible to apply the salicide used in the LOGIC-LSI to the gate electrode.
It was customary in the past to use a polysilicon layer doped with an impurity in the memory LSI. Also, in view of the necessity for decreasing the resistance, employed is a W polycide structure in which a W silicide is laminated on the polysilicon layer. Where the resistance is further decreased, employed is a polymetal structure in which an ultra thin barrier metal layer is formed on the polysilicon layer and a W film is laminated on the barrier metal layer. The polymetal structure has a resistivity lower than that of the structure prepared by laminating a silicide film on the polysilicon layer, making it possible to achieve a desired sheet resistance with a smaller film thickness. However, a dual gate is required in the LOGIC-LSI. Therefore, it is necessary to perform an impurity doping to the polysilicon layer in the gate and to the source-drain regions at different timings, leading to a marked increase in the manufacturing cost.
In an LSI in which a LOGIC and a DRAM are mounted together, if a salicide is attached to the source-drain regions in the DRAM, a pn junction leak current is increased in the memory cell portion, leading to a lowered retaining characteristics. Also, a W polycide is used in the gate electrode because of the particular construction of the SAC structure described above. On the other hand, in the LOGIC, it is necessary to lower the threshold voltage of the MOSFET because current is allowed to flow as much as possible under a low voltage. Such being the situation, the polysilicon of the polycide is doped with P or As in the n-channel MOSFET to use the polysilicon as a n
+
-silicon layer and is doped with BF
3
in the p-channel MOSFET to use the polysilicon as a p
+
-silicon layer.
Incidentally, DRAM requires a large heat budget after formation of the gate electrode. Therefore, in the case of using the gate electrode structure in which a polysilicon layer forms the lowermost layer, two problems given below are generated in the heating step after formation of the gate electrode.
First of all, impurity atoms such as As atoms and P atoms are outwardly diffused from the polysilicon layer into the W silicide layer, leading to reduction in the impurity concentration in the polysilicon layer. As a result, a depletion layer is expanded within the gate electrode in the step of applying voltage so as to deplete the gate. It follows that the gate capacitance is rendered smaller than the actual value determined by the gate insulating film.
A second problem is that boron atoms within the polysilicon layer are diffused through the gate insulating film so as to reach the silicon substrate. As a result, the distribution in the impurity concentration in the channel region is changed so as to change the threshold voltage of the MOSFET. The inward diffusion of the boron atoms (B) is promoted in the case where F or hydrogen are present together with B. Incidentally, where nitrogen is added to the gate insulating film, a B—N bond is formed at the interface between the polysilicon layer and the gate insulating film because the B—N bond is strong, with the result that the inward diffusion of B is suppressed.
The two problems described above can be summarized as follows:
(1) A gate electrode is required independently for each of the LOGIC-LSI and the memory LSI, making it impossible to use a common gate electrode; and
(2) The gate depletion and the inward diffusion of B are generated in the case of employing the polycide or polymetal structure.
Various measures are being proposed for solving the problems given above. For example, proposed is a so-called “metal gate” in which a metal material, not a semiconductor material, is formed directly on the gate insulating film. It is certainly possible to solve the problems derived from the inactivation of the impurities and the impurity diffusion by using the metal gate. However, it is difficult to achieve a precise gate processing in the case of the metal gate.
A method of using a dummy gate is also known to the art. In this method, a dummy gate is formed first, followed by forming source-drain regions and an interlayer insulating film. Then, the surface of the dummy gate is exposed to the outside and the dummy gate is removed, followed by forming a new metal gate film.
Incidentally, the damascene gate process is a process that facilitates the application of the metal gate and an insulating film having a high dielectric constant. However, where the clearance between the contact and the wiring is small and, thus, SAC is required like a high density me
Lindsay Jr. Walter L.
Niebling John F.
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