Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
2001-03-28
2002-10-01
Elms, Richard (Department: 2824)
Static information storage and retrieval
Systems using particular element
Ferroelectric
C365S149000, C365S207000
Reexamination Certificate
active
06459608
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to data reading methods and semiconductor memory devices, particularly to ferroelectric memories using oxide ferroelectric thin films for capacitors.
2. Description of the Related Art
In recent semiconductor memory devices used is a ferroelectric memory called an FRAM in place of a volatile memory such as a DRAM. The ferroelectric memory is a memory using a ferroelectric thin film (PZT film, PLZT film, BTO film, or the like) for a storage element and has such excellent characteristic features that the times of rewrite can be greatly increased, the energy necessary for a rewrite can be reduced, and the rewrite speed can be considerably increased.
There is a ferroelectric memory having such a ferroelectric capacitor integrated on a semiconductor device.
The ferroelectric memory can be formed with almost the same structure as that of a DRAM except that a ferroelectric film is used as the capacitor film (dielectric film) of a memory cell and allows high degree of integration like a DRAM. In addition, since polarization inversion of a ferroelectric material is used, written data is nonvolatile, and can be rewritten at high speed and low power consumption.
The structure and operation of the ferroelectric memory will be described below with reference to drawings.
FIG. 1
shows the hysteresis characteristics of the ferroelectric capacitors C
0
and C
1
. Referring to
FIG. 1
, the abscissa represents the potential of the electrode on the plate line PL side with respect to that of the electrode on the bit line BL
0
or BL
1
side, and the ordinate represents polarization. For the illustrative convenience, points +Pr and −Pr represent the states “0” and “1”, respectively.
As a 2-transistor/2-capacitor memory cell, data “1” corresponds to a state wherein “0” is written in the ferroelectric capacitor C
0
, and “1” is written in the ferroelectric capacitor C
1
, and data “0” corresponds to a state wherein “0” is written in the ferroelectric capacitor C
1
, and “1” is written in the ferroelectric capacitor C
0
.
FIG. 2
is a timing chart showing circuit operation in reading data “1”. This circuit operation in reading data “1” will be described below with reference to FIG.
2
.
First, the potential of the word line connected to the selected cell is raised to turn on the switching transistors. Next, a pulse is input to the plate line PL. Charges move onto the bit line BL
1
due to polarization inversion of the ferroelectric capacitor C
1
, so the potential of the bit line BL
1
rises.
On the other hand, the potential of the bit line BLO does not change because no polarization inversion occurs in the ferroelectric capacitor C
0
. When the sense amplifier
1
is activated (high state) time t
0
′ after from the pulse input, the potential difference between the bit lines BLO and BL
1
is amplified, and data is externally read out. At this time, the data is written in the ferroelectric capacitor C
1
again due to the potential difference between the plate line PL and the bit line BL
1
. Next, a pulse is input to the plate line PL again, thereby writing opposite data in the ferroelectric capacitor C
0
.
However, when data are written in the ferroelectric capacitors C
0
and C
1
and held for a long time, a voltage shift occurs in hysteresis characteristics. This phenomenon is called an imprint effect. When imprinting occurs, polarization in one direction becomes stable. However, when opposite data is written, depolarization occurs to make the data write/read difficult.
FIGS. 3A and 3B
, and
4
A and
4
B show changes in polarization in reading data from an imprinted ferroelectric capacitor. Symbol &Dgr;P
01
and the like in
FIGS. 3A
to
4
B represents a polarization change amount, in which the first numeral indicates the direction of imprinting, and the second numeral indicates data to be read. For example, &Dgr;P
01
means that “1” is written/read in/from a capacitor imprinted in the “0” direction. A write/read of data in the same direction as the imprinting direction is represented by SS (Same State), and a write/read of data in the direction opposite to the imprinting direction is represented by OS (Opposite State). Hence, &Dgr;P
01
and &Dgr;P
10
correspond to OS (Opposite State), and &Dgr;P
00
and &Dgr;P
11
correspond to SS (Same State).
Referring to
FIGS. 3A and 3B
, in the OS (Opposite State), when imprinting progresses, the value &Dgr;P
01
decreases. On the other hand, as shown in
FIGS. 4A and 4B
, in the SS (Same State), the value of polarization change rarely changes. For this reason, when the potential difference between the bit lines BL
0
and BL
1
is to be detected in the OS (Opposite State), the difference between the value &Dgr;P
01
and the value &Dgr;P
10
is detected as a smaller value than in an un-imprinted state because the value &Dgr;P
01
decreases and the value &Dgr;P
10
increases. As imprinting progresses, the difference between the value &Dgr;P
01
and the value &Dgr;P
10
decreases.
FIGS. 5A and 5B
show a change over time in each polarization.
FIG. 5A
shows a signal margin in the SS (Same State).
FIG. 5B
shows a change in signal margin in the OS (Opposite State). As shown in
FIG. 5A
, in the SS (Same State), since the polarization change amount does not vary due to imprinting, the signal margin does not change. However, in the OS (Opposite State), the signal margin changes over time as imprinting progresses. When this margin becomes lower than the read capability of the circuit, the data read is disabled. This determines the service life of a device.
Such an imprint effect is an inherent phenomenon caused by the hysteresis characteristics of a ferroelectric film and therefore cannot be completely suppressed. This imprinting makes it impossible to read desired data and also limits the service life of a device.
As described above, an FRAM has excellent characteristics that nonvolatile data can be written, and can be rewritten at high speed and low power consumption. However, when a shift due to the imprint effect occurs in the hysteresis characteristics of the capacitor, a data read error occurs, and the service life is shortened.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a data reading method and a semiconductor memory device, which allow a data read with a minimum read error by ensuring an output margin necessary for the read and improve the service life of a device even when imprinting occurs in a ferroelectric memory using a ferroelectric film and the polarization change amount varies.
According to the present invention, there is provided a data reading method of reading data stored in a ferroelectric capacitor having one electrode connected to a plate line and the other electrode connected to a bit line through a selecting transistor, by inputting a pulse to the plate line and then performing sense operation to amplify the data. The sense operation is performed after a signal is output from the bit line on the basis of the pulse, and the signal output is decreased from a peak value.
According to another aspect of the data reading method of the present invention, the signal output is decreased by ensuring a predetermined time from input of the pulse to the sense operation.
According to the present invention, there is also provided a semiconductor memory device for reading stored data by the above-described data reading method, wherein a data read or write is performed while an imprint effect of the ferroelectric capacitor is reduced in a refresh or every predetermined time or every predetermined number of times of read.
The present invention comprises the above technical means. Even when imprinting occurs in the hysteresis of a ferroelectric film formed in the ferroelectric memory, and the signal output from the non-switching capacitor (data “0”) becomes larger than a normal value, unfavorable increase of bit line level can be canceled because the sense operation is performed after the signal output is decreased from th
Arent Fox Kintner Plotkin & Kahn
Fujitsu Limited
Nguyen Tuan T.
LandOfFree
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