Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2001-01-08
2002-10-22
Jackson, Jr., Jerome (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C257S401000
Reexamination Certificate
active
06469316
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor processing, and more particularly to test structures for detecting counterdoping in integrated circuits and to methods of making and using the same.
2. Description of the Related Art
In complimentary metal oxide semiconductor (“CMOS”) circuit structures, n-channel and p-channel transistors are fabricated in huge quantities to implement a large variety of different circuit structures on a semiconductor substrate. In many cases, the p-channel and n-channel transistors are fabricated in relatively close proximity, there being a physical separation between the two devices only by a trench isolation structure or field oxide region. In many conventional fabrication processes, the transistor gate electrodes for both the p-channel and n-channel devices are fabricated from polysilicon lines that are patterned from a bulk deposited polysilicon film. Thereafter, the polysilicon gates are rendered conductive by either source/drain region impurity implants or by a separate implant dedicated to gate doping.
Early CMOS transistor pairing involved the n-type or p-type doping of both the p-channel and n-channel field effect transistor gates. More modem techniques routinely involve the implanting of p-channel transistor gate electrodes with p-type impurities and the n-channel transistor gates with n-type impurities, usually through the use of alternating masking of the p-channel and n-channel active regions. In addition, a so-called “poly pre-doping” implant is sometimes performed on the n-channel transistor gate electrodes in order to further enhance their performance, that is, to improve their threshold voltage and drive current characteristics.
In conventional practice, the poly pre-doping of n-channel devices is accomplished by applying a photoresist layer, usually negative tone, and thereafter forming an opening in the resist using standard lithography techniques. The layout of the mask opening will generally overlap substantial portions of the n-channel transistor gate electrodes. However, particularly in those circumstances where the n-channel and p-channel devices share a common polysilicon line functioning as a transistor gate electrode, there exists the propensity for diffusion of n-type impurities longitudinally through the shared transistor gate electrode from the n-channel side toward the p-channel devices. This diffusion of n-type impurities into the device regions of the p-type transistors may lead to a counterdoping of the p-type transistor gates and an attendant skewing of the threshold voltage and/or other operating characteristics of the p-channel transistors.
While the extent of opposite conductivity type impurity diffusion toward the p-channel devices following the poly pre-doping implant is a function of several parameters, one critical factor is the location of the edge of the polysilicon pre-doping photomask opening relative to the p-channel transistors. Currently, the relative spacing between p-channel devices and the edge of a poly pre-doping mask opening for the n-channel transistor poly pre-doping implant is determined empirically and involves some degree of guess work. Obviously, if the amount of diffusion of n-type impurities toward the p-channel device regions is greater than anticipated, counterdoping and device performance drop off may be the unintended result.
The present invention is directed to overcoming or reducing the effects of one or more of the foregoing disadvantages.
SUMMARY OF THE INVENTION
In accordance with one aspect of the present invention, a test circuit is provided that includes a semiconductor substrate and a mask on the substrate that has an opening with an edge. The opening is to enable impurity doping of selected portions of the test circuit. A plurality of circuit devices are provided on the substrate. The circuit devices have respective active regions positioned at staggered known distances from the edge of the mask opening. Each of the plurality of circuit devices has a predicted on-state output current, a first source/drain region and a second source/drain region of a first conductivity type, and a gate electrode that extends to the opening and has a first impurity region of the first conductivity type and a second impurity region of a second and opposite conductivity type. Where the predicted on-state output current of a given circuit device exceeds an actual output current of the given circuit device, there is indication of an overlap between the first and second impurity regions of the gate electrode of the given device.
In accordance with another aspect of the present invention, a test circuit is provided that includes a semiconductor substrate and a mask on the substrate that has an opening with an edge. The opening is to enable impurity doping of selected portions of the test circuit. A plurality of field effect transistors are provided on the substrate that have respective active regions positioned at staggered known distances from the edge of the opening. Each of the plurality of field effect transistors has a predicted on-state output current, a first source/drain region and a second source/drain region of a first conductivity type, and a gate electrode that extends to the opening and has a first impurity region of the first conductivity type and a second impurity region of a second and opposite conductivity type. Where the predicted on-state output current of a given field effect transistor exceeds an actual output current of the given field effect transistor, there is indication of an overlap between the first and second impurity regions of the gate electrode of the given field effect transistor.
In accordance with another aspect of the present invention, a method of semiconductor processing is provided that includes forming a plurality of circuit devices on a semiconductor substrate with respective active regions positioned at staggered known distances from a reference line on the substrate. Each of the plurality of circuit devices has a predicted on-state output current, a first source/drain region and a second source/drain region of a first conductivity type, and a gate electrode. The gate electrode is formed with a first impurity region of the first conductivity type located over the active region. A mask is formed on the substrate that has an opening that exposes portions of each of the plurality of gate electrodes and an edge substantially coincident with the reference line. The exposed portions of each of the gate electrodes are implanted with an impurity of a second and opposite conductivity type to establish a second impurity region therein. The substrate is annealed to diffuse impurities of the second impurity regions toward the first impurity regions. The predicted on-state output current is compared with the actual output current for each of the plurality of circuit devices. Where the predicted on-state output current exceeds the actual output current of a given circuit device, there is indication of an overlap between the first and second impurity regions of the gate electrode of the given device.
REFERENCES:
patent: 5986283 (1999-11-01), Bush et al.
patent: 6232619 (2001-05-01), Chen
Stanley Wolf and Richard N. Tauber;Silicon Processing for the VLSI Era,vol. 2—Process Integration; pp. 298-313, 66; 1990.
Brown David E.
Bush John J.
Gardner Mark I.
Advanced Micro Devices , Inc.
Honeycutt Timothy M.
Jackson, Jr. Jerome
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