Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-10-06
2002-08-27
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C703S015000, C702S067000, C702S073000, C702S079000, C702S118000, C702S125000
Reexamination Certificate
active
06442741
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to methods for analyzing integrated circuits (ICs) during design of those ICs or during failure analysis of those ICs during development. More particularly, present invention relates to a new and improved method of automatically identifying instances of close or unacceptable signal timing skew (signal timing differences) and/or close or unacceptable timing margins (set up and hold times) that might cause or be the cause of functional problems with the IC under differing conditions of temperature, voltage and process. The first above identified invention is utilized with the present improvements in defining a logic cone or rearward extending group of only the relevant circuit components or cells of the IC which cause a particular output signal at a predetermined output signal transition time and the input signals to each relevant cell that predict the functionality of that cell in the cone, to enable the present invention to analyze those cells and their input predictors for close or unacceptable skew and margin. Analysis of the IC during design and failure analysis is facilitated.
BACKGROUND OF THE INVENTION
Most modern semiconductor integrated circuits (ICs) are extremely complex in the number and interconnection of their components or cells. The complexity results from a number of trends in modern electronics. For example, the continual miniaturization of ICs allows more functional cells to be placed on the same sized chip for essentially no additional cost. The cost of an IC is generally related only to the physical size of the substrate upon which the IC is formed and not to the number of components of the IC. Therefore, the effort is to include more cells and functionality in each new IC. The trend in electronics has also been toward integrating entire systems into a single chip, or at least toward integrating larger portions of entire systems into single chips. Such ICs are called application-specific integrated circuits (ASICs) or system level integrated circuits (SLICs). Moreover, most ASICs and SLICs have multiple layers of electrical conductors formed on top of the functional elements of the substrate which connect the various components. These layers of interconnects are also sufficiently complex as to themselves be sources of function-influencing factors of the ASIC or SLIC.
Fabricating a modern, complex IC, such as an ASIC or SLIC, is also a complicated task. The fabrication involves designing the schematic circuitry by using specific cells and connecting them in certain manner, and then simulating the functionality of the schematic circuitry to determine whether the circuitry meets the functional objectives. The design and the simulation are so complex that both functions are generally performed by computer programs or tools designed for those specific purposes. For example, the circuit itself is designed by the use of a behavioral level language, which defines the all of cells in the circuit and their connectivity, and in doing so creates a file known as a netlist which describes those cells and their connectivity. A schematic viewing tool obtains information from the netlist to create a visual display of the circuit and its components. To test the functionality of the circuit, a Verilog simulation program is used. The Verilog simulation program refers to the netlist and additional information which defines the logical function and time delays and other functional factors associated with each of the cells, and develops output state change signals and output transition times for each of the cells in response to a specific input signal. The output state change signals and the output transition times for each of the cells is thereafter displayed by the use of a waveform viewing tool. The waveform viewing tool makes use of the output state change and transition time information derived from the Verilog simulation program to create a display of the waveforms existing at each of the cells in the circuit. The use of behavioral level language circuit synthesis tools and Verilog simulation tools is well-known.
To perform the simulation, the internal functional behavior of each of the cells and the interconnections of the IC are defined within the simulation program. The simulation program also takes into account external influences on the IC from certain variables, such as temperature, voltage and process. The temperature variable takes into account the temperature at which the IC is subjected. In most ICs, when the temperature increases the switching and signal propagation speed of the IC diminishes. The voltage variable relates to the level of voltage of the power applied to the IC. Voltage changes may either increase or decrease the signal switching and propagation times within an particular IC, depending upon the design of the IC. The fabrication process variable refers to signal switching and propagation times differences induced in the IC according to the processing techniques used to build or fabricate the IC. In most cases, the process variable is defined with respect to a nominal process, but slight variations in the fabrication process may result in significant faster or slower signal switching and propagation times than those resulting from nominal fabrication processes.
Many of the logic cells have characteristic performance requirements which must be met in order to achieve reliable and predictable operation. One characteristic timing requirement which applies to synchronous elements, such as flip-flops and clocked latches, is a set up and hold time. A set up time requirement relates to be relative timing between the application of a clock signal and the application of a data signal to the synchronous element. To obtain proper performance of the synchronous element, the data signal must be present and applied to the synchronous element for a certain amount of time prior to the application of the clock signal to that synchronous element. If this set up time requirement is violated, the output signal from the synchronous element is not certain or predictable. The hold time requirement is similar to the set up time requirement, except that the hold time requirement relates to the amount of time that the data signal must be applied to the synchronous element after the clock signal was applied. Again, the purpose of the hold time requirement is to assure a guaranteed and predictable response from the synchronous element. The set up and hold time requirement is frequently referred to as a “timing margin” requirement. The term “race condition” is sometimes used to describe a violation of a set up and hold time requirement. Obviously, race conditions are to be avoided because they are indicative of unpredictable and uncertain functionality.
Another performance characteristic relates not so much to the requirements applicable to the cells themselves, but to the functionality achieved by groups of interconnected cells. Generally speaking, the design of the IC presumes that the signals applied to each of the logic cells will occur in predetermined relationships with respect to other timing events occurring within the IC. Many logic cells require the simultaneous application of numerous signals to achieve proper functionality, and in many cases two or more of those signals must be applied within a certain time window in order for the logic cell to perform its intended to function. The predictable arrival of the signals at the logic cells is the foundation for the logic design of the IC itself. Differences or skew in the timing of the signals therefore has an important and significant impact on the functionality of the IC.
Each simulation takes into account the external variables of temperature, voltage and process. Under those conditions, the proper functionality of the IC is determined, primarily by an indication of whether an output signal or signals behave as expected in response to a selected input signal. So long as the output signal or signals behave properly, the typical simulation does not consider or evaluat
John R. Ley, L.L.C.
Kik Phallaka
LSI Logic Corporation
Smith Matthew
LandOfFree
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