Semiconductor device with self-aligned contact structure

Details Semiconductor device with self-aligned contact structure Semiconductor device with self-aligned contact structure

1999-11-22

2002-11-12

Chaudhuri, Olik (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S383000, C257S412000

Reexamination Certificate

active

06479873

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having a self-aligned contact structure and a manufacturing method thereof.
2. Description of the Background Art
A Self-Aligned Contact (hereinafter simply as “SAC”) in which a contact hole connecting to a source/drain region in a self-aligned manner to a film protecting gate electrode has been used. Since this conventional structure allows a contact hole reaching a source/drain region to be formed without considering the position of a gate electrode, and the structure is therefore essential in reducing the size of the transistor thereby reducing a semiconductor device. The structure has been therefore often employed for conventional DRAMs (Dynamic Random Access Memories). The SAC structure applied for these devices have a refractory metal silicide film on the gate electrode but not on source/drain regions.
In recent years, in order to further improve the performance of the semiconductor devices, efforts have been made to reduce the contact resistance between source/drain regions and contact interconnections. Therefore, a contact structure having a refractory metal silicide film both on the surfaces of source/drain regions and a gate electrode came to be a mainstream, particularly in logic-based devices.
In conventional salicide process where the entire surface of a silicon substrate is covered with a refractory film, followed by a heat treatment to cause the silicon to react with the refractory metal, so that the refractory metal silicide film is formed both on the surfaces of the source/drain regions and the gate electrode at a time, a protection film to cover the gate electrode cannot be formed. Therefore, a contact hole to connect to the source/drain region cannot be formed with the protection film covering the gate electrode. This is because a method of manufacturing a semiconductor device according to the conventional salicide process is as follows. A conventional method of manufacturing a semiconductor device where the upper surface of a gate electrode and the upper surface of source/drain regions are formed into silicide at a time will be now described in conjunction with
FIGS. 25
to
40
.
An isolation oxide film
102
to isolate an element forming region is formed on a p-type silicon substrate
101
. A silicon oxide film
104
as thick as 3 nm for example to be a gate insulating film is formed in the element isolation region. Then, a polycrystalline silicon film
103
as thick as 200 nm is formed on silicon oxide film
104
and the state as shown in
FIG. 25
is attained. As shown in
FIG. 26
, resist film
108
is patterned on polycrystalline silicon film
103
. Using resist film
108
as a mask, etching is performed until a surface of silicon oxide film
104
to be a gate oxide film is exposed, followed by removal of resist film
108
, and polycrystalline silicon film
103
forming a gate electrode as shown in
FIG. 27
is attained.
Using polycrystalline silicon film
103
as a mask, an impurity to form a source/drain region
110
is implanted, and then a sidewall insulating film such as a sidewall silicon nitride film
109
is formed. Then, an impurity to form a source/drain region
111
is implanted to form an LDD (Lightly Doped Drain), and the state as shown in
FIG. 28
is attained.
Then, a heat treatment is performed with a refractory metal film covering the entire surface of silicon substrate
101
to form a refractory metal silicide film
106
on the upper surface of polycrystalline silicon film
103
and on the upper surface of source/drain
111
, a gate electrode
136
is formed, followed by removal of a non-reacted part of refractory metal film, and the state as shown in
FIG. 29
is attained.
An NSG (Non Doped Silicate Glass) film
114
is formed to cover the entire surface of silicon substrate
101
. Then, a silicon nitride film
115
is formed on NSG film
114
. A BPSG (Boro-Phospho Silicate Glass) film
116
is formed on silicon nitride film
115
. Then, the surface of BPSG film
116
is subjected to CMP (Chemical Mechanical Polishing) and flattened, and the state as shown in
FIG. 30
is attained.
After forming a pattern of a resist film on source/drain regions
110
and
111
to form contact holes
131
and
132
, etching is performed until a surface of silicon nitride film
115
is exposed. Then, contact holes
131
and
132
are further deepened so as to sequentially etch silicon nitride film
115
and NSG film
114
, etching is performed until a surface of refractory metal silicide film
106
is exposed, and the state as shown in
FIG. 31
is attained. Contact plugs
131
a
and
132
a
are formed to fill contact holes
131
and
132
, and the state as shown in
FIG. 32
is attained.
In a semiconductor device having a conventional SAC structure manufactured according to the manufacturing method described above, as shown in
FIG. 31
, a film to serve as a protection film cannot be formed on gate electrode
136
when contact hole
131
is formed. If therefore the position to form contact hole
131
reaching refractory metal film
106
on source/drain regions
110
and
111
is shifted to the side of gate electrode
136
, not only a surface of refractory metal silicide film
106
on source/drain regions
110
and
111
, but also a surface of refractory metal silicide film
106
on gate electrode
136
is exposed. Thus, as shown in
FIG. 32
, when contact plug
131
a
is filled in contact hole
131
, gate electrode
136
and source/drain regions
110
and
111
could be short-circuited.
Therefore, a silicon nitride film to serve as a protection film may be previously formed on gate electrode
136
. A method of manufacturing a semiconductor device according to which such a silicon nitride film to serve as a protection film is formed on the gate electrode will be described in conjunction with
FIGS. 33
to
40
.
Until the state shown in
FIG. 25
is attained, the same steps as the manufacturing method described above are performed. As shown in
FIG. 33
, a silicon nitride film
107
is formed on polycrystalline silicon film
103
. Then as shown in
FIG. 34
, resist film
108
is patterned on silicon nitride film
107
. Then using resist film
108
as a mask, etching is performed until a surface of silicon oxide film
104
to be a gate oxide film is exposed, followed by removal of resist film
108
and silicon nitride film
107
to protect polycrystalline silicon film
103
to form a gate electrode as shown in
FIG. 35
is formed.
Using polycrystalline silicon film
103
and silicon nitride film
107
as masks, an impurity to form source/drain region
110
is implanted, and a sidewall insulating film such as a sidewall silicon nitride film
109
is formed on the sidewalls of polycrystalline silicon film
103
and silicon nitride film
107
. Then, an impurity to form source/drain region
111
is implanted to form an LLD (Lightly Doped Drain) structure and the state as shown in
FIG. 36
is attained.
With a refractory metal film being deposited to cover the entire surface of silicon substrate
101
, a heat treatment is performed to form a refractory silicide film
106
only on the upper surface of source/drain region
111
, then a non-reacted part of the refractory metal film is removed, and the state as shown in
FIG. 37
is attained.
An NSG film
114
, a silicon nitride film
115
and a BPSG film
116
are sequentially formed to cover the entire surface of silicon substrate
101
in the same steps as those in the conventional manufacturing method according to which a protection film on the gate electrode, and the state as shown in
FIG. 38
is attained.
A resist film is patterned to form contact holes
131
and
132
reaching refractory metal silicide film
106
on source/drain region
111
, and then BPSG film
116
, silicon nitride film
115
, and NSG film
114
are sequentially formed on the gate electrode similarly to the conventional manufacturing method according to which a protection film is not formed on the gate electrode, and the state

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