Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-02-07
2002-10-08
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S106000
Reexamination Certificate
active
06461953
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a solder bump forming method for forming solder bumps on substrates of various kinds, to an electronic component mounting method, and to an electronic component mounting structure.
As used herein, the term “substrate” is not limited to the narrow definition of printed circuit boards, wafers, and the like, but is defined broadly to include all manner of materials permitting formation of solder bumps thereon.
BACKGROUND ART
Demand for ever higher electronic component mounting densities in recent years has led to a switch in electronic component mounting processes from face-up techniques employing wire bonding to face-down techniques using solder bumps. Typical conventional methods for solder bump formation include plating processes and vapor deposition processes. Such methods, however, have the drawback of requiring large and expensive equipment, and do not allow for easy control of solder bump height and solder composition.
Past proposals for solving this problem include the use of heat-resistant insulating film (JP-A-1-161850) and the use of sheets (JP-A-9-116257).
Referring to accompanying
FIG. 9
a
, according to the solder bump forming method of JP-A-1-161850, a board
9
on which solder bumps are to be formed has as structure wherein a glass film surface layer
92
has been formed covering the aluminum metallization
91
on the surface of the board proper
90
, and electrodes
94
have been situated within recesses
93
provided in this surface layer
92
. To form solder bumps on board
9
, first, an insulating film
95
is formed over surface layer
92
as shown in
FIG. 9
b
. This insulating film
95
is formed by applying a liquid resin over the entire surface of surface layer
92
and electrodes
94
and then etching the resin from the surfaces of the electrodes
94
. By this process recesses
93
′ that are deeper than recesses
93
are formed above electrodes
94
. Recesses
93
′ are then filled with solder paste
5
e
as shown in
FIG. 9
c
, and the solder is then heated to re-melt it, and then hardened. With this method, the depthwise dimension of recesses
93
′ is increased by formation of a dielectric layer
95
over surface layer
92
allowing the amount of solder paste packed into recesses
93
′ to be increased. As a result, it is possible to produce protruding solder bumps
50
, as shown in
FIG. 9
d.
However, the method depicted in
FIGS. 9
a
-
9
d
has a number of drawbacks, such as the following. Since dielectric layer
95
is formed over surface layer
92
by a process of applying a liquid resin over the entire surface of surface layer
92
and electrodes
94
and then etching portions thereof, it is difficult to accurately produce a finished dielectric layer
95
having predetermined thickness t throughout. It is accordingly a difficult matter to ensure that the plurality of recesses
93
′ have uniform depth at all locations, and this tends to result in significant variation in height of the plurality of solder bumps
50
formed subsequently. Height variation of solder bumps
50
is undesirable in terms of achieving electrical interconnection with other components via the solder bumps.
Where solder bumps are utilized for electrical interconnection with other components, it is sometimes necessary to use large amounts of solder in order to make the solder bumps as tall as possible. With the conventional method described above, however, there exists a certain limit as to the thickness t of the insulating film
95
that can formed by application of liquid resin, and this in turn prevents recesses
93
′ from being made very deep. It is accordingly difficult to form solder bumps
50
of height exceeding a certain given height. A further drawback of the conventional method is that if is attempted to increase total insulating film thickness by forming an additional insulating film layer over insulating film
95
in the same manner, the liquid resin becomes thickly applied in recesses
93
′ as well during application of the resin to produce the dielectric layer, and it is difficult to properly etch the resin in these areas.
The solder bump forming method disclosed in JP-A-9-116257, on the other hand, employs a sheet
8
having openings
80
therein, as shown in
FIG. 10
a
. To form solder bumps, a mask sheet
81
is first superposed on sheet
8
as shown in
FIG. 10
b
, using the mask sheet
81
to pack solder paste
5
f
into the openings
80
of sheet
8
. The mask sheet
81
is then separated from sheet
8
as shown in
FIG. 10
c
. Next, as shown in
FIG. 10
d
, sheet
8
is arranged on a substrate
82
with solder paste
5
f
situated over electrodes
83
. Heating and re-melting solder paste
5
f
in this state produces solder bumps
51
as shown in
FIG. 10
d
. Sheet
8
is subsequently removed from substrate
82
as shown in
FIG. 10
f
. This method allows sheet
8
to be reused in a plurality of solder bump forming operations, and additionally allows depth and diameter of openings
80
of sheet
8
to be made uniform throughout.
However, the conventional method depicted in
FIGS. 10
a
-
10
f
requires prefabrication of a sheet
8
having a plurality of openings
80
corresponding in arrangement to the arrangement of the plurality of electrodes
83
on substrate
82
. Further, fabrication of sheet
8
requires an operation totally separate from the process for forming electrodes
83
on substrate
82
. Thus, in addition to the labor entailed in fabricating sheet
8
, fabrication of sheet
8
becomes increasingly difficult at the smaller pitch of the plurality of electrodes
83
needed for smaller integrated circuit patterns. Smaller pitch of the plurality of electrodes
83
also results in reduced precision of alignment of the plurality of electrodes
83
and the plurality of openings
80
in sheet
8
. As a result, this latter method has the drawback of difficulty in precisely aligning solder paste
5
f
over electrodes
83
at smaller pitches of the plurality of electrodes
83
, and poses the risk of unwanted conduction between adjacent solder bumps
51
,
51
.
JP-A-7-273439 discloses a solder bump forming method whereby the drawbacks of the two preceding conventional methods may be overcome. The solder bump forming method disclosed in this publication involves first forming a first solder resist layer on the surface of a board having a circuit pattern formed thereon, and then etching this first solder resist layer to produce openings in locations corresponding to the locations of electrodes in the circuit pattern. A second solder resist layer is then applied to the surface of the first solder resist layer, and this second solder resist layer is etched to produce openings in locations corresponding to the openings in the first solder resist layer. The openings in the two solder resist layers are then filled with solder paste, which is heated/re-melted and then hardened to produce solder bumps on the electrodes in the circuit pattern. Finally, the second solder resist layer is dissolved away using a dissolving liquid that dissolves the second solder resist layer without dissolving the first solder resist layer.
With this method, the thickness of the first solder resist layer and the thickness of the second solder resist layer are utilized to create greater depth in the recesses (the openings formed by the two solder resist layers) into which the solder paste is packed, thus allowing solder bumps of sufficient size to be formed. Since the first solder resist layer remains after the second solder resist layer has been dissolved away, shorting between solder bumps is prevented, so the process is adaptable to finer pitch between electrodes.
According to the method disclosed in JP-A-7-273439, however, if the board and the second solder resist layer are based on the same type of resin, the board will partially dissolve during the process of dissolving the second solder resist layer, resulting in defects. Further, the need for a process to dissolve away the second solder re
Sakuyama Seiki
Uchida Hiroki
Fujitsu Limited
Nelms David
Nhu David
LandOfFree
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