Low dielectric constant materials for copper damascene

Details Low dielectric constant materials for copper damascene Low dielectric constant materials for copper damascene

1999-07-02

2002-08-20

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S758000, C438S769000, C438S778000, C438S780000, C438S786000, C438S790000

Reexamination Certificate

active

06436824

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to a method of metallization in the fabrication of integrated circuits, and more particularly, to a method of dual damascene metallization in the manufacture of integrated circuits.
(2) Description of the Prior Art
The damascene or dual damascene process has become a future trend in integrated circuit manufacturing, especially in the copper metallization process. These processes are discussed in
ULSI Technology,
by Chang and Sze, The McGraw Hill Companies, Inc., NY, N.Y., c. 1996, pp. 444-445. In the copper damascene scheme, the conventional etch stop and passivation, or barrier, layers comprise silicon nitride which has a dielectric constant of about 7. One of the ways to reduce capacitance is to introduce an etch stop layer and a barrier layer having a low dielectric constant.
U.S. Pat. No. 5,858,869 to Chen et al discloses an intermetal dielectric layer using anisotropic plasma oxides and low dielectric constant polymers. U.S. Pat. No. 5,880,018 to Boeck et al shows a dual damascene process in which the top dielectric layer has a low dielectric constant. The layer comprises a spin-on-polymer or spin-on-glass or other low dielectric constant material such as HSQ. U.S. Pat. No. 5,648,200 to Letize et al discusses photoimageable dielectrics using organosilanes as conditioners. U.S. Pat. No. 5,759,906 to Lou shows a variety of conventional low dielectric constant materials. U.S. Pat. No. 5,523,163 to Ballance et al teaches the use of Si—O containing low dielectric constant materials.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method of metallization in the fabrication of integrated circuit devices.
Another object of the invention is to provide a dual damascene metallization process using low dielectric constant materials.
Yet another object of the invention is to provide low dielectric constant materials for the dual damascene process.
Yet another object of the invention is to provide low dielectric constant materials as the passivation layer or etch stop layer in the dual damascene process.
In accordance with the objects of this invention novel low dielectric constant materials for use as dielectric in the dual damascene process are provided. A low dielectric constant material dielectric layer is formed by reacting a nitrogen-containing precursor and a substituted organosilane in a plasma-enhanced chemical deposition chamber.
Also, in accordance with the objects of the invention, novel low dielectric constant materials for use as a passivation or etch stop layer in the dual damascene process are provided. A carbon-doped silicon nitride passivation or etch stop layer having a low dielectric constant is formed by reacting a substituted ammonia precursor and a substituted organosilane in a plasma-enhanced chemical deposition chamber. Alternatively, a silicon-carbide passivation or etch stop layer having a low dielectric constant is formed by reacting a substituted organosilane in a plasma-enhanced chemical deposition chamber.
Also, in accordance with the objects of the invention, a process of forming passivation, dielectric, and etch stop layers for use in the dual damascene process is achieved. An interconnection line is provided through an insulating layer on a semiconductor substrate. A carbon-doped silicon nitride or silicon carbide passivation layer is deposited overlying the insulating layer and interconnection line. A first dielectric layer is deposited overlying the passivation layer wherein the first dielectric layer has a dielectric constant less than three. The first dielectric layer is cured. Thereafter, a carbon-doped silicon nitride or silicon carbide etch stop layer is deposited overlying the first dielectric layer. A second dielectric layer is deposited overlying the etch stop layer wherein the second dielectric layer has a dielectric constant less than three. The second dielectric layer is cured. An optional capping layer of carbon-doped silicon nitride or silicon carbide is deposited overlying the second dielectric layer. A dual damascene opening is formed through the second dielectric layer, the etch stop layer, the first dielectric layer, and the passivation layer to the interconnection line. A barrier metal layer and a copper layer are formed within the dual damascene opening to complete copper metallization in the fabrication of an integrated circuit device.


REFERENCES:
patent: 5523163 (1996-06-01), Ballance et al.
patent: 5605867 (1997-02-01), Sato et al.
patent: 5648200 (1997-07-01), Letize et al.
patent: 5759906 (1998-06-01), Lou
patent: 5858869 (1999-01-01), Chen et al.
patent: 5880018 (1999-03-01), Boeck et al.
patent: 6159871 (2000-12-01), Loboda et al.
Chang et al., “ULSI Technology”, The McGraw-Hill Companies Inc., New York, c. 1996, pp. 444-445.

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