Semiconductor memory device having regions with independent...

Details Semiconductor memory device having regions with independent... Semiconductor memory device having regions with independent...

2001-05-02

2002-10-22

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S230030, C365S230060, C365S230080

Reexamination Certificate

active

06469947

ABSTRACT:

FIELD OF THE INVENTION
The present invention generally relates to semiconductor memory devices having refresh functions. The device is operable with double wordline activation in which wordlines belong to different memory blocks of 2N (N is an integer) rows each other are enabled at the same time during a refresh operation for NK (K is 2
10
) wordlines.
BACKGROUND OF THE INVENTION
Dynamic random access memory (DRAM) is usually exposed to leakage current flowing its substrate in which memory cells are constructed, and thereby contains weak data retention facility relative to other memory devices. Therefore, it is basically necessary for the DRAM to employ a refresh function that re-writes data into memory cells before losing the data stored in the memory cells. In the refresh operation, data weakly stored in the memory cells are read out therefrom and restored therein after being amplified. The DRAM generally manages the refresh operation with reiterate cycling modes that are conductive by a predetermined time.
The refresh operation starts with transition of row address strobe signal/RAS. from its precharge state of high level to low level, which activates wordlines, and then with activation of sense amplifiers. Memory cells coupled to the selected wordlines are simultaneously refreshed (i.e., their ordinary data are renown).
A cycle of the refresh operation is defined within the period when the row address strobe signal /RAS is laid on low level after receiving addresses for refreshing. The refresh cycle is usually dependent on the number of unit cycles to complete the data renewing for memory cells associated with all of rows in a DRAM, being represented to as the number of wordlines activated to perform the refresh operation for all of memory cells.
Conventional DRAMs are designed with bonding options alternatively adaptable to refresh modes of NK (N is integer; K 2
10
that is the number of wordlines for refreshing) or 2NK. The DRAM is embedded on one of boards associated with the refresh modes of NK and 2NK. The NK refresh mode is programmed into “H” (i.e., high level) while the 2NK is set into “L” (i.e., low level), by means of the bonding option.
Being operable either in the refresh modes of NK or 2NK by the bonding option, the DRAMs are oriented to be conductive with readout/write-in operations according to the 2NK refresh mode as usual.
FIG. 1
illustrates a row chain in conjunction with an architecture of memory array in a general DRAM. The first buffer
10
receives row address signal ADD
—
2NK and refresh command signal NK-REFRESHB and then converts them into CMOS logic from the external TTL logic. The row address signal ADD
—
2NK, including its complementary, is to designate block sets BS divided into two, and the refresh command signal NK-REFRESHB enables a refresh mode in the DRAM. The second buffer
12
receives block selection address signals ADD_BLOCK<
1
:log
2
n>(n is the number of blocks), including their complementary signals, and converts it into CMOS logic. The third buffer
14
transfers wordline selection address signals ADD_WL<
1
:
2
i
>
0
(i is the number of bits forming thereof), including their complementary signals, into the device with CMOS logic. The wordline selection address signals ADD_WL<
1
:
2
i
> make one of wordlines belong to a block be activated.
When the refresh command signal NK_REFRESHB is low level, the row address signals ADDX
—
2NK and ADDXBhd —2NK (the complementary signal of ADDX
—
2NK) from the first buffer
10
are compressed and set into high levels. The high-level established row address signals ADDX
—
2NK and ADDXB
13
2NK are applied to block control unit
20
together with the block address signals ADDX_BLOCK and ADDXB_BLOCK (the complementary signal of ADDXB_BLOCK) provided from the second buffer
12
through the fourth buffer
16
. The block control unit
20
selects an alternative one of 2N blocks B with the row address signal ADD
—
2NK that has been compressed into a pattern to divide the block sets into two designable sets. The wordline selection address signals ADDX_WL and ADDXB_WL (the complementary signal of ADDX_WL) from the third buffer
14
are applied to decoder
22
through the fifth buffer
18
, and then provided to the two blocks B. Main X-decoders MWL
—
1 through MWL
—
2n enables wordlines arranged in cell arrays
24
a,
24
b,
24
c,
and
24
d
those are included in the two blocks B.
FIG. 2
shows a pattern of the row address signal ADD
—
2NK to designate cell arrays of a 2NK block set into two groups each of the groups is 1NK wordlines (N is the number of the cell arrays of a NK block, and K is the number of wordlines of a cell array). The 2NK block set is formed of two NK block sets. Bit patterns of addresses to designate the cell arrays CELL ARRAY
1
~N are arranged from
00
..
01
to
11
..
11
. The row address signal ADD-2NK to distinguish the two block sets (i.e., dividing the memory cell array into two groups each of which is 1NK) is assigned to the most significant bit “0” for the first INK block set or “1” for the second INK block set. The rest bits of the address bit arrangement are for the block selection address signals ADD_BLOCK. During the NK refresh mode, as the row address signal ADD
—
2NK is compressed into a unified bit (or regarded to as an invalid bit), a pair of the cell arrays (one is in the first 1NK block set, and the other is in the second 1NK block set) is selected at the same time by corresponding block addresses ADD_BLOCK. For example, one of the block address,
00
..
01
. activates two of the CELL ARRAY
1
of the two 1NK block sets for the NK refresh mode.
As aforementioned, when the refresh modes for NK and 2NK are alternatively operable in the conventional DRAM by employing the bonding option, the number of wordlines enabled in the NK refresh mode becomes twice during read-out and write-in operations because one of address bits (e.g., the ADD
—
2NK) is rendered to be not utilized therein. Comparing such a feature of the NK refresh mode with that of the 2NK refresh mode, current dissipation in the NK refresh mode is more than two times of that in the 2NK refresh mode due to the doubled number of the wordlines. The enlarged number of the wordlines activated at the same time in the NK refresh mode causes access speed of reading or writing data to be lowered.
SUMMARY OF THE INVENTION
Accordingly, it is a primary object of the invention to provide a semiconductor memory device capable of reducing current consumption during a refresh mode.
It is another object of the invention to provide a semiconductor memory device capable of enhancing data access speed during a refresh operation by reducing the number of wordlines activated at the same time.
For the purpose of achieving the those objects, a semiconductor memory device according to the invention includes a block set having a plurality of cell array blocks which each is divided into a plurality of regions which employ wordlines independently from each other, row driving means to alternatively select the wordlines arranged each in the regions, and column driving means to activate columns of the cell arrays involved in the wordlines selected by the row driving means.


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