Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Incorporating resilient component
Reexamination Certificate
2001-04-23
2002-08-13
Sherry, Michael J. (Department: 2829)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Incorporating resilient component
C438S106000, C438S127000
Reexamination Certificate
active
06432746
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
This invention relates to a semiconductor packaging technology, and in particular to a method for manufacturing chip scale packages.
2. Description of Related Art
It has long been desired to produce semiconductor chips that are lighter, smaller, and having higher speed, multi-function and improved reliability at low costs. Various packaging technologies have been developed to address these needs. For example, a ball grid array (BGA) package provides a relatively high surface-mount density and improved electrical performance as compared to conventional plastic packages having a metal lead frame.
The BGA package is different from a conventional plastic package in that the electrical connection between the semiconductor chip and the main board is provided by a substrate including multiple layers with circuit patterns instead of the lead frame of the plastic packages. In the BGA package, the semiconductor chip is attached and electrically connected to a substrate having vias that interconnect electrically conductive traces on the top of the substrate where the chip is attached to terminals on the bottom of the substrate opposite the chip. The terminals on the bottom of the substrate can be provided in an array pattern so that the area occupied by the BGA package on a main board is smaller than that of the conventional plastic package with peripheral terminals.
The substrate used in the BGA package, however, may still be larger than the semiconductor chip because an area without conductive traces may be required when attaching the chip to the substrate. A further reduction in the size of the BGA package may thus be limited. In response, the further size reduction of semiconductor chip packages have been provided by a chip scale package (CSP, also referred to as ‘chip size package’).
In recent years, various CSP models have been introduced by several semiconductor manufacturers in the USA, Japan and Korea, and the development for the new form of the CSP is under way. Among them, the micro-BGA (&mgr;BGA) is a representative chip scale package developed by Tessera. The micro-BGA employs a tape-wiring substrate such as a thin flexible circuit board. One of the characteristics of the micro-BGA is that beam leads are bonded to bond pads of the semiconductor chip through a window formed in the tape-wiring substrate all at the same time.
However, as the semiconductor chip scales further down, it has become more difficult for the micro-BGA to accommodate fine pitch and arrangement of the bond pads in two rows. In response to these problems, a wire-bonding-type CSP has been introduced. The wire-bonding-type CSP applies a wire-bonding technology to ensure reliability of the CSP by replacing beam lead bonding of the micro-BGA with the wire bonding. The wire-bonding-type BGA can be manufactured through the same process, except for wire bonding and plasma cleaning steps.
FIG. 1
shows a cross-sectional view of conventional wire-bonding-type chip scale package.
To an active surface of a semiconductor chip
10
, a substrate
40
is attached by a non-conductive adhesive
30
. On the surface of the substrate
40
is formed a wiring pattern
50
, which may be of copper. A photosensitive resin layer
60
is deposited and patterned. The photosensitive resin layer
60
is used to prevent the neighboring patterns from being short-circuited and burnt during test processes such as a THB (thermal humidity bias) test. Each solder ball
70
is bonded to a corresponding solder ball land
55
, which is formed by patterning the wiring pattern
50
and the photosensitive resin layer
60
. Bonding wires
80
electrically connect the semiconductor chip
10
and the wiring pattern
50
. Thereafter, the bonding wire areas of the semiconductor
10
are encapsulated with an encapsulant
90
.
However, in the conventional wire-bonding-type CSP
100
, the loop height of the bonding wire
80
is higher than that of the photosensitive resin layer
60
. Therefore, the encapsulant
90
rises above the top surface of the photosensitive resin layer
60
. This results in an overflow of the encapsulant
90
into the solder ball land
55
, although not shown in FIG.
1
. If this happens, before the solder balls
70
are attached to the solder ball lands
55
, the overflowed encapsulant
90
can be stuck to the attached solder balls
70
. This weakens the bonding between the solder balls
70
and the solder ball lands
55
. At worst, this may result in physical detachment of the solder balls
70
from the solder ball lands
55
. Also, an electrical resistance in the solder joint can be increased and testing of the CSP can fail when test pins are repeatedly closed and opened to pick and release the solder balls
70
contaminated with the overflowed encapsulant
90
.
SUMMARY OF THE INVENTION
Accordingly, it is an object of this invention to provide a method for manufacturing a chip scale package having a structure capable of preventing an overflow of an encapsulant.
It is another object of this invention to provide a method for manufacturing a chip scale package, which can overcome the problem of burning of neighboring patterns.
According to one aspect of this invention, a method for manufacturing a chip scale package (CSP) including a semiconductor chip and conductive bumps is disclosed. In one embodiment of the present invention, a flexible substrate is provided with a conductive pattern formed thereon. The substrate has a top surface and a bottom surface. Then, a first photosensitive resin pattern is formed over the top surface of the substrate. Next, the first photosensitive resin pattern is cured. Subsequently, a second photosensitive resin pattern is formed over the cured first photosensitive resin pattern. The second photosensitive resin pattern includes a slit comprising a bottom of the first photosensitive resin pattern and side walls of the second photosensitive resin pattern.
These and other features, and advantages, will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings. It is important to point out that the illustrations may not necessarily be drawn to scale, and that there may be other embodiments of this invention, which are not specifically illustrated.
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patent: 6093970 (2000-07-01), Ohsawa et al.
patent: 6210992 (2001-04-01), Tandy et al.
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patent: 1999-001899 (1999-01-01), None
patent: 1999-0191076 (1999-06-01), None
English abstract of Korean Patent No. 1999-0191076B.
English abstract of Korean Patent No. 1999-001899A.
Choi Hee-Guk
Kim Se Ill
Kim Shin
Oh Se Yong
Geyer Scott
Marger Johnson & McCollo, P.C.
Samsung Electronics Co,. Ltd.
Sherry Michael J.
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