Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-10-26
2002-12-31
Elms, Richard (Department: 2824)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S296000, C257S298000, C257S310000, C257S535000
Reexamination Certificate
active
06501112
ABSTRACT:
BACKGROUND OF THE INVENTION
a) Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same. More specifically, the present invention relates to a semiconductor device and a method of manufacturing the same represented by a non-volatile semiconductor memory (FeRAM: Ferroelectric Random Access Memory) using a ferroelectric material for the dielectric film of a capacitor, or a volatile semiconductor memory (DRAM: Dynamic Random Access Memory) using a high dielectric material for the dielectric film of a capacitor, or a LSI system incorporating these memory elements and logic elements.
b) Description of Related Art
In recent years, the use of ferroelectric material for the dielectric film of a capacitor with respect to a FeRAM is attracting attention as a low power consuming non-volatile semiconductor memory. Additionally, the ultra-miniaturization and high integration density of semiconductor memory are more and more in demand. As such, DRAM using a high dielectric material for the ferroelectric film of a capacitor has been developed to satisfy such a demand.
Generally, metal oxide films are used for the ferroelectric material of a FeRAM and for the high dielectric material of a DRAM.
The ferroelectric material and the high dielectric material are easily influenced and easily deteriorate with regard to the polarization characteristic.
Next, the related art of FeRAM will be explained. The related are of FeRAM provides a ferroelectric capacitor formed by sequentially laminating: a lower electrode, for example, consisting of Pt (Platinum); a ferroelectric film consisting of PZT; and a upper electrode consisting of Pt, on the insulation film. An interlayer insulation film is formed to cover the ferroelectric capacitor and an aluminum wiring is then formed thereon. In order to protect these films, a passivation film consisting of a silicon oxide film and a silicon nitride film are then formed.
However, since the pattern of the aluminum wiring is formed thickly in the passivation film of the related art, the level differences of the projection and the recesses at the surface of the passivation film formed thereon is large.
Moreover, when level differences of the projection and the recesses at the surface of the passivation film is large and the interval of aluminum wiring is narrow, a cavity is generated between the wirings. Particularly, in the case where the passivation film is formed with the plasma enhanced CVD method, the level differences of the projection and the recesses at the surface of passivation film is easily increased.
This cavity exists at the region where the wiring interval becomes wide. And on the occasion of forming a contact hole using the resist mask in order to form the pad later, the resist explodes because the gas trapped in the cavity is released at the region near the ending point of the cavity.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a semiconductor device and a method of manufacturing the same which prevents local explosion of resist formed on the passivation film which is formed on the capacitor using ferroelectric material or high dielectric material, and also prevents deterioration of the capacitor.
One aspect of the present invention provides a semiconductor device comprising a transistor formed on a semiconductor substrate, a capacitor formed on a first insulation film covering the transistor, a wiring layer formed on the capacitor via the second insulation film and a passivation film covering the wiring layer. The passivation film is formed of a first silicon oxide film, a nitride film is formed on the first silicon oxide film, and a second silicon oxide film is formed on the nitride film.
According to the present invention, the cavity formed in the nitride film, used as the passivation film, is covered with a second silicon oxide film. The gas staying in the cavity is not released in the post-process, and thus, the local explosion of resist can be prevented.
In particular, as the second silicon oxide film, a passivation film including the silicon oxide film (TEOS-O
3
film) has been formed with ozone (O
3
) and TEOS using the CVD method.
This TEOS-O
3
film assures high coverage and may be formed at the growth temperature as low as 300° C. Therefore, degasification is not generated from the nitride film deterioration of capacitor characteristic. Meanwhile, the silicon oxide film (P-TEOS film) formed using the plasma enhanced CVD method with TEOS gas is inferior for coverage compared to the TEOS-O
3
film, and cannot perfectly cover the cavity as explained above. Moreover, since the P-TEOS film is formed at a temperature as high as about 400° C., degasification is generated from the nitride film and deteriorates the capacitor's characteristic.
However, the TEOS-O
3
film includes more moisture in the film in comparison with the P-TEOS. film. To eliminating such moisture, the dehydration process of the TEOS-O
3
film is executed with plasma annealing, for example, of an N
2
O gas or an NO gas in the present invention.
When an electric furnace is used during the heat treatment for dehydration, the annealing in the electric furnace is limited, for example, to the temperature identical to the heat resistant temperature of 450° C. of aluminum because a metal wiring layer is provided as the lower layer of the passivation film. However, sufficient dehydration effect cannot be attained only with such heat treatment. When plasma annealing is performed, as in the case of the present invention, moisture is eliminated from the insulation film at the temperature of 450° C. or less. Therefore, the problem that the metal wiring layer is oxidized will never occur in such a temperature.
Therefore, moisture in the passivation film can be eliminated more effectively with the plasma annealing process in comparison with only heat treatment. Additionally, ferroelectric film and high dielectric film reduction, together with capacitor deterioration resulting from moisture in the passivation film, can be prevented. Thus, high quality FeRAM or DRAM may be manufactured.
According to the plasma annealing of N
2
O gas or NO gas, nitrogen is included at least to the surface of the TEOS-O
3
film. Nitrogen introduced into the TEOS-O
3
film is capable of blocking the entry of moisture from the external side, and thereby, improve the humidity resistance thereof.
REFERENCES:
patent: 5475248 (1995-12-01), Takenaka
patent: 5745336 (1998-04-01), Saito et al.
patent: 5990507 (1999-11-01), Mochizuki et al.
patent: 6017784 (2000-01-01), Ohta et al.
patent: 6046490 (2000-04-01), Arita et al.
Arent Fox Kintner & Plotkin & Kahn, PLLC
Elms Richard
Menz Douglas
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