Semiconductor device

Details Semiconductor device Semiconductor device

1999-12-16

2002-11-26

Thomas, Tom (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S348000, C257S349000

Reexamination Certificate

active

06486513

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a silicon-on-insulator metal-oxide semiconductor transistor (hereinafter referred to as an SOIMOS transistor), more particularly relates to a technique for suppressing a floating-body effect in the transistor.
2. Description of the Background Art
Great attention is now focused on SOIMOS transistors as high-speed, low-power devices and their application to LSI for portable equipment for example is expected.
A conventional SOIMOS transistor, however, has its body in a floating state, thus producing a parasitic bipolar effect that one type of carriers which are produced by impact ionization in the vicinity of the drain (e.g., holes for n-type SOIMOS transistors and electrons for p-type SOIMOS transistors) are accumulated in the vicinity of the source, whereby a parasitic bipolar transistor comprised of source, body, and drain enters into its active state. This produces a kink effect of reducing a threshold voltage of the SOIMOS transistor and thereby causing a sudden local change in drain current in the vicinity of certain drain voltage (voltage applied between source and drain) and causes a problem of reducing a drain breakdown voltage. If impurity concentration in the channel region is increased to suppress reduction in the threshold voltage of the SOIMOS transistor due to the parasitic bipolar effect, current driving capability and speed performance of the transistor are degraded.
To suppress the parasitic bipolar effect, various techniques for preventing the accumulation of carriers in the vicinity of the source of an SOIMOS transistor have been proposed. In the following description, an n-type SOIMOS transistor is taken as an example, but the same applies to a p-type SOIMOS transistor.
FIG. 22
is a cross-sectional view showing the structure of a conventional SOIMOS transistor. On a buried oxide film
2
formed on a semiconductor substrate
1
, an SOI layer
4
, which is to be a body along with a channel region, is formed and a source
51
and a drain
52
are formed through the SOI layer
4
. The source
51
and the drain
52
have for example LDD (Lightly Doped Drain) structures. The SOI layer
4
sandwitched between the source
51
and the drain
52
is opposed to a gate electrode
7
with a gate oxide film
6
including sidewalls in between. On the outer side of the source
51
and the drain
52
, a trench isolation oxide film
31
is provided through the SOI layer
4
.
For such an SOIMOS transistor, a first conventional technique for preventing the accumulation of holes in the vicinity of the source
51
is to implant argon ions in the vicinity of the boundary between the source
51
and the buried oxide film
2
to thereby produce lifetime killers. This technique is introduced for example by T. Ohno et. al. in the article entitled “Suppression of the Parasitic Bipolar Effect in Ultra-Thin-Film nMOSFETs/SIMOX by Ar Ion Implantation into Source/Drain Regions,” Tech. Dig. IEDM, 1995, pp.627-630.
FIG. 23
is a cross-sectional view showing the case where a salicide (self-aligned silicide) structure is applied to the structure of FIG.
22
. In contrast to the structure of
FIG. 22
, silicide layers
58
,
59
,
79
are formed on the source
51
, the drain
52
, and the gate electrode
7
, respectively.
FIG. 24
is a cross-sectional view showing another structure of a conventional SOIMOS transistor. In contrast to the structure of
FIG. 22
, the source
51
and the drain
52
include germanium-implanted regions
81
and
82
, respectively, which are formed in the surface (upper surface) of the SOI layer
4
on the opposite side of the buried oxide film
2
. The source
51
and the drain
52
are for example formed of silicon and thus the components of the regions
81
and
82
are Si—Ge. in a second conventional technique presenting such a structure, distortion of the band structure occurs between source and body. This technique is introduced for example by M. Yoshimi et. al. in the article entitled “Suppression of the Floating-Body Effect in SOIMOSFET's by the Bandgap Engineering Method Using a Si
1−x
Ge
x
Source Structure,” IEEE Trans. Electron Devices, vol. 44, 1997, pp. 423-429.
In either of the first and second conventional techniques, however, the source
51
and the drain
52
reach the buried oxide film
2
through the SOI layer
4
, so a problem of the impracticability of suppressing a “diffraction electric field” still remains. Similar structures are also disclosed in other references such as Japanese Patent Laid-open No. P08-130315A.
FIG. 25
is a cross-sectional view illustrating a “drain electric field through the buried oxide”. When a predetermined voltage is applied to the gate electrode
7
and a higher potential than that on the source
51
is imposed on the drain
52
, a depletion layer
91
is formed and an electric field
101
is generated from the drain
52
through the buried oxide film
2
to the channel region
4
. Hereinafter, this is called the “diffraction electric field”.
With the “diffraction electric field,” a drain-induced barrier lowering (DIBL) effect becomes noticeable. This DIBL effect is a kind of short channel effect that a source-side potential barrier varying with drain voltage reduces the threshold value of a transistor. The occurrence of the “diffraction electric field” should preferably be prevented especially in an element with the buried oxide film
2
, such as an SOIMOS transistor.
There is also proposed a structure in which neither the source
51
nor the drain
52
reach the buried oxide film
2
through the SOI layer
4
.
FIG. 26
is a cross-sectional view showing still another structure of a conventional SOIMOS transistor. In contrast to the structure of
FIG. 22
, the source
51
and the drain
52
are formed within the SOI layer
4
so that their bottoms are kept from contact with the buried oxide film
2
. This allows drawing of holes from the opposite side of the gate electrode
7
with respect to the source
51
, through the remaining SOI layer
4
between the source
51
and the buried oxide film
2
. Such a third conventional technique is introduced for example by Y.-H.Koh et al. in the article entitled “Body-Contacted SOI MOSFET Structure and Its Application to DRAM,” IEEE Trans. Electron Devices, vol. 45, 1998, pp. 1063-1070, and also in Japanese Patent Laid-open No. P05-67785A.
This structure, however, requires a body terminal for drawing holes and the formation of a body terminal may cause an area penalty. Further, effects achieved by the method for drawing holes through a body terminal vary according to the location of a body contact region; therefore, a problem of pattern dependence arises.
In
FIG. 26
, the ends of a depletion layer
92
are within the SOI layer
4
, failing to reach the buried oxide film
2
since drain voltage is small. If the drain voltage is more than a predetermined value, the ends of the depletion layer
92
would reach the buried oxide film
2
, causing a voltage drop across the depletion layer along with reduction in junction capacitance. This may lower voltage across the buried oxide film
2
, thereby reducing the intensity of the “diffraction electric field”. Junction capacitance in the source also needs to be reduced because it is to be the cause for reduction in the operating speed when the source potential is lowered.
SUMMARY OF THE INVENTION
A first aspect of the present invention is directed to a semiconductor device comprising: an insulating layer; a semiconductor layer of a first conductivity type provided on the insulating layer; first and second impurity layers of a second conductivity type opposite to the first conductivity type, which are provided apart from each other in an upper surface of the semiconductor layer so as to be kept from contact with the insulating layer; and an electrode opposed to a portion of the upper surface of the semiconductor layer which is sandwiched between the first and second impurity layers, with an insulation film in between, wherein a depletion la

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