Method and apparatus for supporting multi-clock propagation...

Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation

Reexamination Certificate

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Reexamination Certificate

active

06347351

ABSTRACT:

FIELD OF THE INVENTION
The present invention pertains to computer systems. More particularly, the invention pertains to increasing the length between components coupled via a hub interface.
BACKGROUND OF THE INVENTION
Since the advent of computer systems, there has been a continuous push to reduce production costs in order to provide quality systems at reduced monetary values. One major factor that increases production costs is the expense associated with inter-chip connections. The number of pins that are necessary to make chip connections increase production costs of a computer system. As a result, there is an ever-increasing demand to make inter-chip connections fast and narrow. One example of a fast and narrow interconnect is the hub interface.
A hub interface is an input/output (I/O) interconnect for connecting I/O hubs and Peripheral Component Interconnect (PCI) bridges adhering to a Specification Revision 2.1 bus developed by the PCI Special Interest Group of Portland, Oreg., to a memory controller hub. A Hub interface is a half-duplex bus with a distributed arbiter. Synchronization on the interface occurs by a global clock and two request (REQ) signals. Agents at each side of the interface assert REQ signals to convey a request to the other agent. For example, one agent (e.g., side A) sends a request signal to the other agent (e.g., side B), while side B transmits a request to side A. The REQ signals are sampled at each side, and a decision is made as to which side will be granted access of the interface.
FIG. 6
is a block diagram of an exemplary hub interface. The hub interface includes agent A and agent B coupled by request signals (REQA and REQB) and a data component. Each agent includes an arbiter. The arbiters arbitrate for ownership of the hub interface. The assertion of either an REQA signal or a REQB signal is an arbitration event. At each arbitration event, the arbiters within examine both the REQA and REQB signals and determine ownership of the hub interface independently and simultaneously. When the hub interface is idle, the first of either agent A or B to assert its request wins ownership. If agents A and B request ownership simultaneously when the hub interface is idle, the least recently serviced hub agent wins ownership.
Typical hub interfaces assume that all signals propagate to the opposite end in less than one base clock cycle (including the effect of clock-to-out and setup times). However, there may be certain applications (e.g., server systems) in which the desired length of a hub interface segment has more than a one clock of end-to-end delay (i.e., hub interface is longer). On the other hand, keeping the end-to-end delay to a single clock cycle limits the clock rate, and hence the bandwidth. Therefore, it would be advantageous to develop a method and mechanism to increase the length of hub interfaces without sacrificing system performance.
SUMMARY OF THE INVENTION
According to one embodiment, a computer system comprises a first agent, a point to point half duplex interface coupled to the first agent and a second agent coupled to the point to point half duplex interface. The first agent delays arbitration of a request to access the point to point half duplex interface until the access request is received at the second agent, and the second agent delays arbitration of a request to access the point to point half duplex interface until the access request is received at the first agent.


REFERENCES:
patent: 5682508 (1997-10-01), Hocker
patent: 5915101 (1999-06-01), Kleineberg et al.
patent: 6145039 (2000-11-01), Ajanovic et al.
patent: 6256697 (2001-07-01), Ajanovic et al.
patent: 4426123 (1996-02-01), None
patent: 0552507 (1993-07-01), None
PCT Search Report, PCT/US 00/26875, 3 pages, Mar. 15, 2001.

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