Floating gate isolation device

Details Floating gate isolation device Floating gate isolation device

2000-08-15

2002-11-12

Fahmy, Wael (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Including dielectric isolation means

C257S409000, C257S501000, C257S510000, C257S506000, C257S523000, C438S454000, C438S430000, C438S424000, C438S400000, C438S259000

Reexamination Certificate

active

06479880

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to semiconductor memory devices, and more specifically to trench and field isolation of memory cells in such devices.
BACKGROUND OF THE INVENTION
The growing demand for increasingly smaller semiconductor memory devices having large memory capacities capable of high speed operation has pushed the development of miniaturized memory cell structures in Dynamic Random Access Memory devices (DRAMs). DRAMs, which are capable of inputting and outputting data at random, generally comprise an array of memory cells for storing data and peripheral circuits for controlling data in the memory cells. Each memory cell in a DRAM stores one bit of data and consists of one transistor and one capacitor. Within the array, each memory cell must be electrically isolated from adjacent memory cells.
The degree to which large numbers of memory cells can be integrated into a single integrated circuit (IC) chip is effected primarily by the size of the transistors and capacitors in and the isolating structures between memory cells. The miniaturization of DRAM memory cell transistors and capacitors to 0.35 micron and smaller field width or active area spacing has created the need for corresponding miniaturization of the isolating structures. It is this need for smaller isolating structures that the present invention addresses.
Currently, memory cell isolation is achieved using an oxide film formed by the Local Oxidation Of Silicon (LOCOS) or recessed LOCOS methods, trench isolation, or field isolation. Using LOCOS, a relatively thick oxide region is formed around each cell. As the size of the cell structure is reduced, the corresponding reduction in the size of the oxide region creates several problems. First, for submicron cell spacing, the oxide thinning that occurs with miniaturization is detrimental to isolation. Second, the oxide film regions become the smallest mask feature in the array and, therefore, limit scaling/miniaturization. Third, the field oxide regions form the largest step height in the array. This effects the intermediate BPSG insulation layer and increases the aspect ratio (height to width) of the metal contact, making it more difficult to etch the contact hole. Fourth, in the LOCOS method, an oxide projection commonly referred to as a “bird's beak” forms at the periphery of the thick oxide region and extends into the area in which the cell is formed. The bird s beak reduces the area available for cell formation. This problem is exacerbated by the fact that the size of the bird's beak remains constant even as the size of the LOCOS oxide region is reduced. For these various reasons, the LOCOS method impedes miniaturization of the memory cell array particularly below about 0.35 micron spacing.
Trench isolation utilizes a trench etched into the substrate between memory cells. The trench must have sufficient width and depth to create a physical barrier to current conduction between cells. As the cell spacing is reduced below about 0.35 microns, the aspect ratio of the trench necessary for isolation becomes severe so that it is difficult to etch the trench to the required depth.
Field shield isolation utilizes a shielding electrode formed over the substrate between the source and drain regions of adjacent memory cells. Cell isolation is achieved by applying a low potential to the shielding electrode to prevent current conduction between adjacent memory cells. However, because the shielding electrode occupies space above the substrate in the memory cell array, it is an impediment to further miniaturization. In addition, isolation in the memory cell array for submicron spacing is only achieved as long as a voltage is being applied to the shielding electrode.
A similar method used to overcome the disadvantages of LOCOS in EPROMs and Flash EEPROMs involves replacing the LOCOS regions with EPROM cells. This method of isolation and corresponding structure is described in an article entitled,
A Novel Isolation Scheme for Implementation in Very High Density AMG EPROM and FLASH EEPROM Arrays
, MICROELECTRONIC ENGINEERING, Vol. 19, pp. 253-6 (1992). The EPROM isolation cells disclosed therein are floating gate devices within the array. The programming sequence determines whether any given cell will be a memory cell or an isolation cell. This method uses the high programming voltage already available in the flash circuit. As with field shield isolation, the EPROM isolation structure occupies space in the array above the substrate. In addition, the isolation cell provides isolation in only one direction. LOCOS isolation must also be used to provide isolation in the perpendicular direction to achieve two dimensional isolation.
The present invention is directed to minimizing or eliminating the disadvantages of the LOCOS, trench and field shield isolation structures currently used in the art for cell spacing at or below about 0.35 microns.
SUMMARY OF THE INVENTION
It is therefore a principal object of the present invention to provide an isolation structure and method for forming the same that effectively isolates cells in very small cell spacing to allow high density integration of IC chips.
It is another object to combine the advantages of field isolation and trench isolation in a single isolation structure to provide effective isolation between cells in very small cell spacing.
It is another object to provide an isolation structure that effectively isolates cells in field width or active area spacing on the order of 0.1-0.25 microns.
It is another object to provide isolation in two dimensions in the memory cell array.
It is, another object to provide a field isolation structure that requires only periodic charging to maintain its isolation characteristics.
The above objects are achieved by an isolation structure for semiconductor memory devices comprising a trench formed in the substrate. The trench is lined with insulating material and filled with polysilicon. An electrical charge is then injected into the polysilicon. This isolation structure can be located between memory cells in the array and, thus, provide effective isolation between cells in very small spacing by combining the characteristics of trench and field isolation. The trench in the present invention need not be as deep or as wide as that required for conventional trench isolation because the physical isolation of the trench is enhanced by the field isolation of the charged polysilicon. Unlike conventional field isolation wherein the shielding electrode occupies space above the substrate in the array area of the device, the shielding electrode component is buried in the substrate, thus providing effective isolation in very small cell spacing.
In another aspect of the invention, the electrical charge is injected into the polysilicon by means of the wordlines of the memory cell array. In this aspect of the invention, the surface of the polysilicon in the trench is made substantially coplanar with the top of the trench and overlayed with insulating material to form a floating gate. A layer of polysilicon overlays the insulating layer above the floating gate. The layer of polysilicon will typically be a wordline in a memory cell array having a plurality of wordlines and a plurality of bitlines arranged generally perpendicular to one another over the substrate. An electrical charge is injected into the floating gate by applying a charging voltage to the wordline, whereby Fowler-Nordheim currents are generated in the substrate for charging the floating gate. The charging voltage can then be removed and the wordline used in the operational circuit of the IC chip. The charging voltage need be applied only periodically when the charge on the floating gate falls below a level at which effective isolation can no longer be maintained.
The isolation structure of the present invention will typically be located between adjacent cells in the array beneath and overlapping multiple wordlines. Two dimensional isolation can be achieved by extending the trench to surround each pair of me

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