Multilayered quantum conducting barrier structures

Details Multilayered quantum conducting barrier structures Multilayered quantum conducting barrier structures

2000-06-30

2002-02-05

Thomas, Tom (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S302000

Reexamination Certificate

active

06344673

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to integrated circuits (ICs) and more particularly to multilayered quantum conducting barrier (MQCB) structures for semiconductor devices. MQCB structures find extensive applications in the semiconductor industry to form the buried straps in deep trench cell capacitors.
BACKGROUND OF THE INVENTION
Buried straps (BS) in deep trenches are extensively used in the manufacture of DRAM chips, in particular for devices with groundrules equal or inferior to 0.25 &mgr;m. As known for those skilled in the art, in DRAM chips, an array transfer transistor, typically an insulated gate field effect transistor (IGFET) and a storage capacitor are associated to form an elementary memory cell. Basically, a deep trench having a buried plate surrounding its bottom portion is formed in a doped monocrystalline silicon substrate, then a thin dielectric film is conformally deposited thereon to coat the entire interior trench surface and finally the trench is filled with a doped polysilicon by LPCVD as standard. This doped monocrystalline silicon/dielectric film/doped polysilicon fill structure forms the memory cell capacitor. From the silicon surface, a recess is etched down to set the bottom edge of the buried strap. Undoped polysilicon is then deposited into this recessed area to form the buried strap (BS). The buried strap is bordered by the so-called active area (AA) of the monocrystalline substrate and is buried under the shallow trench isolation (STI) region. The surrounding surfaces of the buried strap have an important effect on its conductivity and solid phase transformation during subsequent oxidation and anneal steps (mainly active area oxidation). During these thermal steps, it occurs a recrystallization of the polysilicon of the region of the buried strap which is contiguous to the active area. This local epitaxy induces the propagation of dislocations along the so-called slip lines into the active area and in the substrate which affect cell capacitor performance. Specifically these defects are believed to cause unpredictable changes of the retention time for the capacitor. More precisely, single cell fails (SCF) occurred in some of the tested memory cells, despite the fact that the same bits were not found defective in previous tests. These defects are called Variable Retention Time (VRT) fails. The VRT problem was first identified for 0.25 &mgr;m DRAM chips where some memory cells in the array intermittently switched from a high retention state to a low retention state. Physical failure analysis (PFA) showed out that the most of analyzed VRT failed memory cells were impacted by these crystal dislocations in the active area and in the substrate that had been formed during said thermal steps in the course of the wafer processing.
To avoid or better control these VRT fails in memory cells, the use of a quantum conducting barrier layer between said contiguous silicon regions becomes an absolute requirement to maximize DRAM chip device performance. As a result, the buried strap will perfectly connect the IGFET and the capacitor of the memory cell only if after said thermal steps (oxidation and anneal), the dopants implanted in the buried strap diffuse into the active area through the quantum conducting barrier. The diffusion depth into the active area is a critical parameter. If the diffusion is too deep, a parasitic vertical transistor (VT) is formed, otherwise some junction leakages occur. Another critical parameter is the buried strap resistance itself which drives the memory cell access time. Consequently, the choice of the quantum conducting barrier material, the buried strap dopant type and concentration are very important factors for the overall chip reliability.
Starting with the
FIG. 1
structure, a conventional buried strap and its quantum conducting barrier (QCB) formation process will be described in conjunction with
FIGS. 2A-2F
.
FIG. 1
schematically illustrates the starting structure
10
consisting of a p-type silicon substrate
11
with a conventional pad stack formed by a 5 nm thick SiO
2
layer
12
and a 220 nm thick Si
3
N
4
pad layer
13
. As apparent in
FIG. 1
, a deep trench referenced
14
has been formed in the substrate
11
by RIE etching as standard. Typically, deep trench
14
has a depth about 7 &mgr;m and an oblong section of about 450×220 nm at the substrate surface. Afterwards, the capacitor dielectric layer
15
is formed and the deep trench is filled with doped polysilicon material
16
. After anneal the doped polysilicon fill
16
is recessed to a depth of 1.2 &mgr;m to allow the formation of a thermal SiO
2
layer
17
and a TEOS SiO
2
(pyrolitic) layer
18
forming the so-called collar layer
17
/
18
which provides a vertical isolation of the cell capacitor. The TEOS layer
18
is etched down to the remaining Si
3
N
4
pad layer
13
. Then, a second doped polysilicon layer
19
is deposited, annealed and polished down to the remaining Si
3
N
4
pad layer
13
. Polysilicon layer
19
is then recessed 130 nm under the substrate
11
surface. This sets the bottom edge of the buried strap. The collar layer
17
/
18
is removed from the upper part of the deep trench
14
exposed by a BHF HUANG A/B solution in a DNS 820 tool (Dai Nippon Screen, Yasu, Japan). This isotropic wet etch will recess the oxide materials of collar layer
17
/
18
slightly under the polysilicon layer
19
level as apparent in FIG.
1
. At last, a angled phosphorous implant is performed in the trench sidewall that is exposed to create region
20
which is part of the active area. This step is followed by a 200:1 DHF pre clean in a CFM tool (sold by CFM, Westchester, Pa., USA) to remove 3 nm of the native SiO
2
layer. The next steps, i.e. the buried strap and its QCB formation must be performed very quickly e.g. within 1 hour (Q-time) of said pre clean step otherwise a rework would be necessary. In fact, this short processing time is required to avoid native oxidation of the exposed silicon substrate
11
.
Now, turning to
FIG. 2A
, a 1.5 nm thin oxide QCB layer
21
is formed by thermal oxidation at exposed silicon surfaces in a LPCVD vertical thermal reactor (VTR) during boat insertion under ambient atmosphere. The QCB layer
21
is made of thermal SiO
2
, a material which is an electrical insulator by nature, however, when deposited in very thin film it becomes electrically conductive by a quantum mechanical effect. An adequate reactor is the baseline undoped polysilicon VTR 7000+ manufactured by SVG THERMCO, Orange, Calif., USA.
The current working conditions are:
N2 load lock : no
Q-time: 1 hour
Boat pitch: 0.14 inch
Batch size: 100 wafers centered
Insert temp.: 620° C.
Insert time: 10 min
It is important to notice that an uncontrollable oxidation rate is the main drawback of this step.
Now referring to
FIG. 2B
, a 300 nm thick undoped polysilicon layer
22
is deposited in the same LPCVD VTR tool. As mentioned above, this undoped polysilicon layer
22
is amorphous and will subsequently form the buried strap.
The working conditions are:
Deposition temp.: 550° C.
Deposition press.: .2 Torr
Deposition time: 167 min
SiH
4
flow: 260 sccm
Deposition rate: 18 Å/min
The SiO
2
QCB layer
21
will reduce recrystallization (epitaxial regrowth) of the amorphous silicon forming the buried strap and the number of dislocations nucleating at the region
20
/polysilicon layer
22
interface. The QCB layer
21
thickness is critical because it has to be thick enough to prevent VRTs and parasitic vertical transistors (VTs) but thin enough to be conductive to insure low buried strap resistance. Consequently, the extreme positions in the LPCVD boat are forbidden, the goal is to have the oxygen level (dose) in layer
21
ranging from 2.2 10
15
atoms/cm
2
(corresponding to a too thin oxide layer) to 3.0 10
15
atoms/cm
2
(corresponding to a too thick oxide layer). In these conditions the batch size in the LPCVD VTR tool mentioned above is limited to 100 wafers centered in the boat.
A planarization of the polysilicon la

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