Semiconductor device and method of manufacturing same

Details Semiconductor device and method of manufacturing same Semiconductor device and method of manufacturing same

2001-03-26

2002-12-24

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Introduction of conductivity modifying dopant into...

Ion implantation of dopant into semiconductor region

C438S528000

Reexamination Certificate

active

06498077

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device such as DRAMs and a method of manufacturing the same.
2. Description of the Background Art
FIG. 217
is a circuit diagram illustrating a construction of a memory cell of a DRAM. As shown in
FIG. 217
, a capacitor C
1
and an NMOS transistor Q
1
are disposed between terminals P
1
and P
2
. One electrode (a cell plate electrode) of the capacitor C
1
is connected to the terminal P
1
, and the other electrode (a storage node electrode) is connected to one electrode (a source or drain electrode) of the NMOS transistor Q
1
. The gate of the NMOS transistor Q
1
is connected to a terminal P
3
, and the back gate is connected to a terminal P
4
. In general, the terminal P
1
is provided with a fixed potential, the terminal P
2
is connected to a bit line, the terminal P
3
is connected to a word line, and the terminal P
4
serves as a terminal for setting the potential of a well region where the NMOS transistor Q
1
is to be formed. Followings are examples of a memory cell element having a construction of “1 Tr (transistor)+1 capa (capacitor)” shown in FIG.
217
.
FIG. 218
is a plan view illustrating a planar structure of a stack-type memory cell (Type
1
).
FIG. 219
is a sectional view taken along the line A
1
—A
1
in FIG.
218
.
Referring to these figures, an NMOS transistor Q
1
and a capacitor C
1
are formed within a P well region
22
in which elements are isolated by an isolation insulating film
23
. The P well region
22
is selectively formed at an upper layer portion of a semiconductor substrate
21
, as shown in FIG.
220
. With a plurality of isolation insulating films
23
, the P well region
22
is isolated transistor by transistor.
As shown in
FIGS. 218 and 219
, source/drain regions
31
and
32
are selectively formed in the surface of the P well region
22
. A gate oxide films
33
and a gate electrode
34
are formed between the source/drain regions
31
and
32
, and a sidewall
35
is formed on both side surfaces of the gate oxide film
33
and a gate electrode
34
. The NMOS transistor Q
1
is made up of the source/drain regions
31
and
32
, gate oxide film
33
, gate electrode
34
and sidewall
35
.
A storage node electrode
41
-
1
is formed on the source/drain region
31
so as to be electrically connected thereto via a contact hole
40
, an insulating film
42
-
1
is formed on the upper and side surfaces of the storage node electrode
41
-
1
, and a cell plate electrode
43
-
1
is formed on the upper and side surfaces of the insulating film
42
-
1
. The capacitor C
1
is made of up the storage node electrode
41
-
1
, insulating film
42
-
1
and cell plate electrode
43
-
1
.
The storage node electrode
41
-
1
is of a plate structure having a square shape in plan configuration.
FIG. 221
is a plan view illustrating a planar structure of a stack-type memory cell (Type
2
).
FIG. 222
is a sectional view taken along the line A
2
—A
2
in FIG.
221
.
Referring to these figures, a storage node electrode
41
-
2
is formed on a source/drain region
31
of an NMOS transistor Q
1
so as to be electrically connected thereto via a contact hole
40
, an insulating film
42
-
2
is formed on the upper and side surfaces of the storage node electrode
41
-
2
, and a cell plate electrode
43
-
2
is formed on the upper and side surfaces of the insulating film
42
-
2
. A capacitor C
1
is made up of the storage node electrode
41
-
2
, insulating film
42
-
2
and cell plate electrode
43
-
2
.
The storage node electrode
41
-
1
is of a cylindrical structure having a circular shape in plan configuration. The construction of the NMOS transistor Q
1
is the same as that shown in
FIGS. 218 and 219
, and a description thereof is thus omitted.
FIG. 223
is a plan view illustrating a planar structure of a stack-type memory cell (Type
3
).
FIG. 224
is a sectional view taken along the line A
3
—A
3
in FIG.
223
.
Referring to these figures, a storage node electrode
41
-
3
is formed on a source/drain region
31
of an NMOS transistor Q
1
so as to be electrically connected thereto via a contact hole
40
, an insulating film
42
-
3
is formed on the upper and inner surfaces of the storage node electrode
41
-
3
, and a cell plate electrode
43
-
3
is formed on the upper and inner surfaces of the insulating film
42
-
3
. A capacitor C
1
is made up of the storage node electrode
41
-
3
, insulating film
42
-
3
and cell plate electrode
43
-
3
.
The storage node electrode
41
-
3
has a hollow cylindrical structure having a circular shape in plan configuration, and the insulating film
42
-
3
and cell plate electrode
43
-
3
are formed within this cylindrical structure. The construction of the NMOS transistor Q
1
is the same as that shown in
FIGS. 218 and 219
, and a description thereof is thus omitted.
FIG. 225
is a plan view illustrating a planar structure of a stack-type memory cell (Type
4
).
FIG. 226
is a sectional view taken along the line A
4
—A
4
in FIG.
225
.
Referring to these figures, a storage node electrode
41
-
4
is formed on a source/drain region
31
of an NMOS transistor Q
1
so as to be electrically connected thereto via a contact hole
40
, an insulating film
42
-
4
is formed so as to cover the convexoconcave part of the storage node electrode
41
-
4
, and a cell plate electrode
43
-
4
is formed so as to cover the insulating film
42
-
4
. A capacitor C
1
is made up of the storage node electrode
41
-
4
, insulating film
42
-
4
and cell plate electrode
43
-
4
.
The storage node electrode
41
-
4
has a fin structure made up of a convex part having a large square shape in plan configuration and a concave part having a small area in plan configuration. This allows for a more junction capacitance. The construction of the NMOS transistor Q
1
is the same as that shown in
FIGS. 218 and 219
, and a description thereof is thus omitted.
FIG. 227
is a sectional view illustrating a sectional structure of a trench-type memory cell (Type
1
). As shown in the figure, a cell plate electrode
43
-
5
of trench structure is buried within a P well region
22
. The cell plate electrode
43
-
5
is covered at its surroundings with an insulating film
42
-
5
, and a source/drain region
63
is formed so as to cover the surroundings of the insulating film
42
-
5
.
The source/drain region
63
functions as one electrode of the NMOS transistor Q
1
and also functions as a storage node electrode of the capacitor C
1
. Otherwise, the construction of the NMOS transistor Q
1
is the same as that shown in
FIGS. 218 and 219
, and a description thereof is thus omitted.
FIG. 228
is a sectional view illustrating a sectional structure of a trench-type memory cell (Type
2
). As shown in the figure, a cell plate electrode
43
-
6
of trench structure is buried within a P well region
22
. An insulating film
42
-
6
is formed so as to cover the side surface of the cell plate electrode
43
-
6
, and a source/drain region
64
is formed so as to cover part of the surroundings of the insulating film
42
-
6
.
The gate electrode
67
is partially buried in the P well region
22
and is isolated from the cell plate electrode
43
-
6
with an insulating region
70
interposed therebetween. A gate oxide film
66
is formed on one side surface of the gate electrode
67
, and the side surface end of the gate electrode
67
overlaps in part the end of the source/drain region
64
via the gate oxide film
66
.
A sidewall
68
is disposed above the P well region
22
via the gate oxide film
66
and is adjacent to the gate electrode
67
. A source/drain region
65
is formed adjacent to the underside of the sidewall
68
in the P well region
22
.
Thus, an NMOS transistor Q
1
is made up of the source/drain regions
64
and
65
, gate oxide film
66
, gate electrode
67
and sidewall
68
, and a capacitor C
1
is made up of the source/drain region
64
, insulating film
42
-
5
and insulating film
42
-
6
. That is, the source/drain region

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