Semiconductor integrated circuit device

Details Semiconductor integrated circuit device Semiconductor integrated circuit device

2000-01-24

2002-08-06

Lee, Michael G. (Department: 2816)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C326S063000, C326S095000, C326S097000, C326S121000

Reexamination Certificate

active

06429687

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a semiconductor integrated circuit device including synchronously operating logic circuits.
2. Description of the Prior Art
In recent years, with the large scale integration of logic circuits, the difference between propagation delay times of clock signals in a clock tree for driving a synchronous circuit, i.e., the bad influence of clock skew on the high speed operation of the logic circuits, has caused serious problems.
If the large scale integration and scale down of a logic circuit proceeds, the wiring resistance of the logic circuit increases as the decrease of the wiring width thereof, so that the RC delay thereof becomes conspicuous. In such a situation, many techniques for reducing clock skew have been devised. Referring to
FIGS. 11 and 12
, the characteristics of the delay caused by the parasitic RC of wiring will be described below.
FIG. 11
is a circuit diagram of a semiconductor integrated circuit device comprising a clock driver
2
and an RC-distributed network
4
which is driven by the clock driver
2
to serve as a clock wiring and which comprises resistors and capacitors.
FIG. 12
shows the observed waveforms D
1
and D
3
of voltages at nodes
5
and
7
on the RC-distributed network
4
. The wiring lengths from the output S of the clock driver
2
to the nodes
5
and
7
are different. Since the wiring length from the clock driver
2
to the node
7
is longer than that to the node
5
, the voltage waveform D
3
at the node
7
is delayed from the voltage waveform D
1
at the node
5
(see FIG.
12
). As the transition in voltage proceeds, the delay amount increases regardless of the direction of the transition in voltage. Therefore, assuming that a power supply voltage is V
dd
, the delay amount of the waveform D
3
from the waveform D
1
at an intermediate voltage (=(V
H
+V
L
)/2) when the voltage changes from V
L
to V
H
(=V
L
+V
dd
) is T
rm
, the delay amount of the waveform D
3
from the waveform D
1
at a voltage between the voltage V
L
and the intermediate voltage is T
rl
the delay amount of the waveform D
3
from the waveform D
1
at a voltage between the intermediate voltage and the voltage V
H
is T
ru
, the delay amount of the waveform D
3
from the waveform D
1
at the intermediate voltage when the voltage changes from V
H
to V
L
is T
fm
, the delay amount of the waveform D
3
from the waveform D
1
at a voltage between the voltage V
H
and the intermediate voltage is T
fu
, and the delay amount of the waveform D
3
from the waveform D
1
at a voltage between the intermediate voltage and the voltage V
L
is T
f1
, then the following inequalities are established.
T
rl
<T
rm
<T
ru
T
fu
<T
fm
<T
f1
That is, as the transition in voltage proceeds, the delay amount increases regardless of the direction of the transition in voltage.
FIG. 13
is a circuit diagram of a conventional semiconductor integrated circuit device wherein clock loadings
15
1
,
15
2
and
15
3
serving as logic circuits are connected to the nodes
5
,
6
and
7
of the RC-distributed network
4
shown in FIG.
11
.
FIG. 14
shows voltage waveforms D
i
at the inputs of the clock loadings
15
i
(i=1, 2, 3).
Since the wiring lengths from the output S of the clock driver
2
to the nodes
5
,
6
and
7
, to which the clock loadings
15
1
,
15
2
and
15
3
are connected, are different, the propagation of a clock signal is delayed as the clock signal travels from the node
5
to the node
7
as described above, so that the propagation is shown in FIG.
14
. At that time, the propagation time differences T
r12
and T
f12
of the waveform D
2
with respect to the waveform D
1
, and the propagation time differences T
r13
and T
f13
of the waveform D
3
with respect to the waveform D
1
are clock skews.
FIG. 15
shows another conventional semiconductor integrated circuit device. This semiconductor integrated circuit device has the same construction as that of the semiconductor integrated circuit device shown in
FIG. 11
, except that clock receiver circuits
40
1
, and
40
2
are connected to the nodes
5
and
7
, respectively. Furthermore, synchronously operating logic circuits (not shown) are connected to the respective outputs of the clock receiver circuits
40
1
and
40
2
.
Inverter circuits
41
and
42
constituting the clock receiver circuit
40
i
(i=1, 2) are set to have an inversion threshold voltages which is the half of the power supply voltage V
dd
, and
5
have input/output voltage characteristics shown in FIG.
16
A. That is, as shown in
FIG. 16B
, assuming that the gate widths of the p-channel MOS transistor p
1
and n-channel MOS transistor n
1
constituting each of the inverter circuits
41
and
42
are W
p
and w
n
, respectively, a ratio w
p
/w
n
, of the size of the transistor p
1
to the size of the transistor n
1
is determined so that the inversion threshold voltage is V
dd
/2. In this case, assuming that the ratio w
p
/w
n
is R, i.e., w
p
/w
n
=R, then R generally approximates 2.
Assuming that the voltages at the respective inputs of the first stage of inverter circuits
41
1
and
41
2
constituting the clock receivers
40
1
and
40
2
are D
1
and D
3
, respectively, and assuming that the voltages at the respective outputs of the inverter circuits
41
1
, and
41
2
are D
1
B and D
3
B, respectively, then the input voltages D
1
and D
3
change as shown in FIG.
17
(
a
), and the output voltages D
1
B and D
3
B change as shown in FIG.
17
(
b
). That is, since the wiring length from the output of the clock driver
2
to the node
7
is longer than that to the node
5
, the input voltage D
3
has a waveform having obtuse leading and trailing edges in comparison with the waveform of the input voltage D
1
(see FIG.
17
(
a
)). Therefore, a time lag t
rm
at the trailing edge and time lag t
fm
at the leading edge of the output voltage D
3
B with respect to the output voltage D
1
B are substantially the same as the time lags T
fm
and T
fm
of the input voltage, respectively (see FIG.
17
(
a
) and
17
(
b
)). This causes clock skew.
In a typical semiconductor integrated circuit device, the wiring lengths from the clock driver
2
to the nodes, to which the synchronously operating logic circuits or the clock receivers are connected, are fixed, and it is not often possible to reduce the capacities of the clock receiver circuits and so. In order to reduce the above described clock skew in such a case, it is required to increase the wiring width of the clock wiring or to detour to extend the clock wiring of the node near the output of the clock driver so that the delay amount at the node matches with that at the farthest node. In either case, there is a problem in that the layout area increases.
In general, the clock wiring is designed to have a large wiring width to reduce skew, and is laid out around various places on a chip, so that the increase of the wiring width or the introduction of the excessive detour wiring has a great influence on the layout area.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to eliminate the aforementioned problems and to provide a semiconductor integrated circuit device capable of reducing clock skew and preventing an increase in layout area.
In order to accomplish the aforementioned and other objects, according to one aspect of the present invention, a semiconductor integrated circuit device comprises: a clock driver for outputting a clock signal; a clock wiring which is driven by the clock driver for transmitting the clock signal; a plurality of logic circuits which are connected to the clock wiring to be synchronously operated in response to the clock signal; and a plurality of delay circuits, each of which is provided between a corresponding one of the logic circuits and the clock wiring for delaying the clock signal, wherein a delay amount of each of the delay circuits is designed so that the delay amounts of the clock signal fro

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