Memory system capable of supporting different memory devices...

Details Memory system capable of supporting different memory devices... Memory system capable of supporting different memory devices...

1997-02-11

2002-02-05

Kim, Matthew (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Memory configuring

C711S105000, C711S156000, C711S005000

Reexamination Certificate

active

06345348

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory system and a semiconductor memory device used therefor, and more particularly relates to a high speed memory system and a semiconductor memory device for the system achieving high speed transfer of a large amount of data.
2. Description of the Background Art
The performance of a microprocessor has been improved, and the storage capacity of a Dynamic Random Access Memory (DRAM) as a memory device is increasing. However, a large amount of data (including instructions) requested by the microprocessor cannot be transferred at high speed from the DRAM to the microprocessor since the operation speed of the DRAM is slower than that of the microprocessor. Therefore, a high speed memory system has been proposed in which a memory controller/processor and a plurality of DRAMs are connected by a bus, and data are consecutively transferred in synchronization with a clock signal. As one example of the high speed memory system, a memory system employing a high speed memory interface referred to as “Sync Link” will be described in the following.
FIG. 16
is an illustration showing a structure of a general Sync Link memory system. In
FIG. 16
, the memory system includes: a controller
1
; a send link
10
transmitting a request packet output from controller
1
; memories (RAMs)
2
-
0
to
2
-n located in parallel and connected to send link
10
in parallel with each other and executing a designated operation according to the request packet supplied via send link
10
; a sink link
20
commonly coupled to memories
2
-
0
to
2
-n transmitting a response packet read from a selected memory to controller
1
; and a control bus line
12
transmitting a flag flg and a strobe srb which are operation timing signals from controller
1
.
Strobe srb on control signal bus
12
defines an operation speed and an operation timing of controller
1
and memories
2
-
0
to
2
-n, and flag flg indicates the start of a packet transmitted onto send link
10
. Send link
10
transmits the request packet from controller
1
in one direction only, while sink link
20
transfers the response packet output from memories
2
-
0
to
2
-n only in one direction toward controller
1
. The request packet includes a slave ID (identifier) for identifying each of the memories
2
-
0
to
2
-n, a command which instructs an operation to be executed, and information on address and write data, for example. The response packet transferred onto sink link
20
includes only read data in a normal operation.
As for the path along which the request packet is transferred from controller
1
to the memories and the response packet is transferred from the memories via sink link
20
, the length of the packet transferred path for each of memories
2
-
0
to
2
-n is made equal. Accordingly, sink link
20
includes a portion coupled to memories
2
-
0
to
2
-n transferring the response packet output from a selected memory in the direction away from controller
1
, and a portion transferring the response packet in the direction toward controller
1
. The packet transfer path of the same distance allows controller
1
to take the same period of time for each of memories
2
-
0
to
2
-n, from outputting the request packet to obtaining the response packet, and synchronized packet transfer is thus easily implemented.
It is noted that controller
1
may be a processor. In the following description, “memory controller” is used as a term referring to both of a controller controlling the access to memories
2
-
0
to
2
-n and a processor having an operational processing function.
Send link
10
generally has a width of 8 or 9 bits, and sink link
20
has a bit width two times larger than that of send link
10
.
FIG. 17
is a timing chart at the time of data reading of the memory system. Referring to
FIG. 17
, a data reading operation will be described.
At time t
0
, “open.row” request is generated. Prior to sending of an open.row packet at time t
0
, a flag fig is raised from “0” to “1”. Transfer of the packet is instructed by the rise of flag FIG. The open.row packet includes a slave ID (identifier) designating one of memories
2
-
0
to
2
-n, a command indicating the open-row, and an address designating a row to be opened. In the case of the open.row, an addressed row in a designated memory
2
-i is selected. At this time, only a row select operation is performed, and data in a memory cell connected to the selected row is not output. Therefore, there is no output of a response packet on sink link
20
.
At time t
1
, a “read.of.open” request is output. At time t
1
, flag fig is also raised from “0” to “1”, and transfer of a packet is instructed. The “read-of-open” request instructs to select a necessary memory cell out of memory cells connected to the row selected by the open.row command and to read data. In other words, the read.of.open corresponds to an ordinary “page hit” state. The request packet on send link
10
is taken into the addressed memory at both of the rise and fall edges of strobe srb. A time period required for the addressed row to be selected in the addressed memory (corresponding to RAS-CAS delay time tRCD of an ordinary DRAM) is needed between time t
0
and time t
1
.
According to the read.of.open, from the addressed memory, corresponding data in the addressed memory cell is read. The data in the addressed memory cell is sent onto sink link
20
at time t
2
. The time between time t
1
and time t
2
is defined by information included in the request packet. The response packet (read data) onto sink link
20
is taken into controller
1
at one of rise and fall of strobe srb.
The bit width of send link
10
is one half that of sink link
20
, while the sampling rate on send link
10
is two times higher than that of sink link
20
. The data transfer rate is accordingly the same. The request packet and the response packet are transferred respectively on send link
10
and sink link
20
, so that data can be consecutively transferred between the memory controller and the memory by sending the request packet to one memory while sending the response packet to memory controller
1
from another memory.
FIG. 18
is a timing chart representing an operation at the time of data writing in the memory system shown in FIG.
16
. At the time of data writing, transfer of request packet is also indicated by the rise of flag flg from “0”to “1” prior to time t
0
. A request packet instructing the open.row is sent onto send link
10
. An addressed row is selected in an addressed memory by the open.row.
After an elapse of row act time (tRCD), a request packet instructing a write operation is sent at time t
1
. The request packet instructing the write operation includes a slave ID for identifying a memory, write data, a command indicating writing of data, and the number of write data. When the write request packet is sent at time t
1
, data is written to an addressed memory cell (column) on the row selected by the open.row in the addressed memory. In the case of the write.request packet, a data packet is not sent onto the sink link since only the writing of data is executed and there is no sending of the response packet.
At the time of data writing access, only the sending of the request packet is performed using send link
10
. Therefore, the response packet can be sent using sink link
20
in parallel with the data writing operation, and high speed data transfer can thus be possible.
FIGS. 19A and 19B
show structures of packets transmitted and received by the controller.
FIG. 19A
illustrates a request packet. The request packet includes an identifier area
22
storing a slave ID (identifier) for identifying the memory, a command area
24
storing a command instructing an operation to be executed, an information area
26
storing information about, for example, address, time to start a response, number of transfer data byte, and write data.
FIG. 19B
illustrates a structure of a response packet. A response packet
28
is only transmitted acco

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