Method of chemical mechanical polishing

Details Method of chemical mechanical polishing Method of chemical mechanical polishing

2000-07-31

2002-10-01

Rose, Robert A. (Department: 3723)

Abrading

Precision device or process - or with condition responsive...

Computer controlled

C451S041000

Reexamination Certificate

active

06458013

ABSTRACT:

FIELD OF THE INVENTION
This invention relates generally to the field of chemical mechanical polishing (CMP) of semiconductor wafers or substrates. More specifically, the invention relates to a method of chemical mechanical polishing of semiconductor wafers or substrates.
BACKGROUND OF THE INVENTION
The ever-increasing demand for high-performance microelectronic devices has motivated the semiconductor industry to design and manufacture Ultra-Large-Scale Integrated (ULSI) circuits with smaller feature size, higher resolution, denser packing, and multi-layer interconnects. The ULSI technology places stringent demands on global planarity on multiple layers, called Interlevel Dielectric (ILD) layers, which comprise the circuit. Compared with other planarization techniques, the chemical mechanical polishing (CMP) process produces excellent local and global planarization at low cost, and is thus widely adopted in many back-end processes for planarizing inter-level dielectric layers, which are most often silicon dioxide (SiO
2
). In addition to achieving global planarization, CMP is also critical to many emerging process technologies, such as the polishing of copper (Cu) damascene patterns, low-k dielectrics, and shallow trench isolation (STI) structures (Landis et al., 1992; Peters, 1998). The wide range of materials to be polished concurrently or sequentially, however, increases the complexity of the CMP process and necessitates an understanding of the process fundamentals for optimal process design and control.
Despite its extensive use in ULSI manufacturing, the basic material removal mechanisms in CMP are not yet well understood. Long ago, Preston empirically found in glass polishing that the material removal rate (MRR) is proportional to the product of the applied pressure and the relative velocity (Preston, 1927). The Preston equation may be written as
ⅆ
ξ
ⅆ
t
=
k
p
⁢
p
⁢
 
⁢
v
R
where &xgr; is the thickness of the layer removed, t the polishing time, p the nominal pressure, v
R
the relative velocity, and k
p
is a constant known as the Preston constant.
In recent years, it has been demonstrated in many works that the above relation is also valid for metals (Steigerwald et al., 1994; Stavreva et al., 1995 and 1997) and ceramics (Nakamura et al., 1985; Komanduri et al., 1996). To explain this proportionality, researches have attempted to study the material removal mechanisms during the CMP process, and several researchers have proposed particle abrasion (Brown et al., 1981; Liu et al., 1996) and pad asperity contact models (Yu et al., 1993) to elucidate the mechanical aspects of the CMP process. Assuming that wafer/abrasive or wafer/pad is in contact, the applied stress field near the wafer surface results in elastic-plastic deformation of the surface layer and produces wear. Another line of research has focused on the chemical mechanisms of the process (Cook, 1990; Luo et al., 1998). Cook first reviewed the chemical process for glass polishing. He suggested that both surface dissolution under particle impact and the absorption or dissolution of wear particles onto the slurry particles will determine the polishing rate of glass. More recently, a two-dimensional wafer-scale model based on lubrication theory (Runnels and Eyman, 1994) and mass transport has been proposed (Sundararajan et al., 1999). In this model, the wafer is assumed to hydroplane on the pad surface, and the normal load is supported by the hydrodynamic pressure of the viscous slurry film. The polishing rate is determined by the convective mass transport of the chemical species.
Whether material removal is by mechanical, chemical, or chemomechanical interactions in the CMP process, an understanding of the contact condition at the wafer/pad interface is important to process characterization, modeling, and optimization. However, to date there is no explicit methodology in the CMP literature to characterize wafer-scale interfacial conditions with process parameters. Some researchers have assumed that the wafer hydroplanes while being polished, and thus solve the Reynolds equation of lubrication to determine the relations among wafer curvature, applied pressure, relative velocity, slurry viscosity, slurry film thickness, and pressure distribution on the wafer surface (Runnel, 1994; Runnel and Eyman, 1994). Another group has assumed the wafer is in contact, or partially in contact with the pad, and relate the displacement of the wafer to the pad elastic modulus and solve the stress field by the classical contact mechanics model (Chekina et al., 1998). Measurement of the vertical displacement of the wafer relative to the pad seems the most direct prior art technique of identifying the contact condition and determine the slurry film thickness (Mess et al., 1997). However, the compliance of the pad material and that of the back film in the wafer carrier make such measurements unreliable. While some experiments in the hydroplaning mode have been conducted on smaller specimens (Nakamura et al., 1985), it is questionable to scale up the results to a larger size wafer. In general, different applied pressure, velocity, and other experimental conditions employed by the various investigators have resulted in a difficult situation to draw any definitive conclusions regarding the mode of interfacial contact. Thus, it is highly desirable to determine and characterize the primary material removal mechanism during CMW and to provide a CMU process that promote an increased material removal rate (MRR) from the surface of the wafer.
Relevant Literature
References discussing CMP processes in the semiconductor industry include:
Bhushan, M., Rouse, R., and Lukens, J. E., 1995, “Chemical-Mechanical Polishing in Semidirect Contact Mode,”
J Electrochem. Soc.,
Vol. 142, pp. 3845-3851.
Bramono, D. P. Y., and Racz, L. M., 1998, “Numerical Flow-Visulization of Slurry in a Chemical Mechanical Planarization Process,”
Proc.
1998
CMP
-
MIC Conf.
, pp. 185-192.
Brown, N. J., Baker, P. C., and Maney, R. T., 1981, “Optical Polishing of Metals,”
Proc. SPIE,
Vol. 306, pp. 42-57.
Bulsara, V. H., Ahn, Y., Chandrasekar, S., Farris, T. N., 1998, “Mechanics of Polishing,” ASME
Journal of, Applied Mechanics,
Vol. 65, pp. 410-416.
Chekina, O. G., Keer, L. M., and Liang, H., 1998, “Wear-Contact Problems and Modeling of Chemical Mechanical Polishing,”
J. Electrochem. Soc.,
Vol. 145, pp. 2100-2106.
Cook, L. M., 1990, “Chemical Processes in Glass Polishing,”
J. Non
-
Crystalline Solids
, Vol. 120, pp. 152-171.
Cook, L. M., Wang, F., James, D. B., and Sethuraman, A. B., 1995, “Theoretical and Practical Aspects of Dielectric and Metal Polishing,”
Semiconductor International,
Vol. 18, pp. 141-144.
Komanduri, R., Umehara, N., and Raghanandan, M., 1996, “On the Possibility of Chemo-Mechanical Action in Magnetic Float Polishing of Silicon Nitride,” ASME,
Journal of Tribology,
Vol. 118, pp. 721-727.
Kaufman, F. B., Thompson, D. B., Broadie, R. E., Jaso, M. A., Guthrie, W. L., Pearson, D. J., and Small, M. B., 1991, “Chemical-Mechanical Polishing for Fabricating Patterned W Metal Features as Chip Interconnects,”
J. Electrochem. Soc.,
Vol. 138, pp. 3460-3464.
Landis, H., Burke, P., Cote, W., Hill, W., Hoffman, C., Kaanta, C., Koburger, C., Lange, W., Leach, M., Luce, S., 1992, “Intergration of Chemical-Mechanical Polishing into CMOS Integrated Circuit Manufacturing,”
Thin Solid Films,
Vol. 220. pp. 1-7
Liu, C. -W., Dai, B. -T., Tseng, W. -T., and Yeh, C. -F., 1996, “Modeling of the Wear Mechanism during Chemical-Mechanical Polishing,”
J. Electrochem. Soc.,
Vol. 143, pp. 716-721.
Luo, Q., Ramarajan, S., and Babu, S. V., 1998, “Modification of Preston Equation for the Chemical-Mechanical Polishing of Copper,”
Thin Solid Films,
Vol. 335, pp. 160-167.
Nakamura, T., Akamatsu, K., and Arakawa, N., 1985, “A Bowl Feed and Double Sides Polishing for Silicon Wafer for VLSI,”
Bulletin Japan Soc. Precision Engg.
, Vol. 19, pp. 120-125.
Peters, L., 1998, “Pursuing the Perfect Low-k Dielectric,”
Semiconductor International,
Vol. 21, pp.

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