Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-09-29
2002-02-19
Wojciechowicz, Edward (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S309000, C257S310000, C257S532000, C438S244000, C438S255000
Reexamination Certificate
active
06348707
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of manufacturing a semiconductor capacitor. More particularly, the present invention relates to a method of manufacturing a dynamic random access memory (DRAM) capacitor.
2. Description of Related Art
In general, each integrated circuit memory unit has a capacitor. The charge level of the capacitor is used to represent a bit of data in the memory. For example, a dynamic random access memory (DRAM) normally consists of an array of memory cells with each memory cell having a charge storage capacitor connected to the source/drain terminal of a pass field effect transistor (FET). The electrode of the capacitor provides one or two different charge levels to represent a logic signal ‘1’ or ‘0’ in the memory cell.
Therefore, the capacitor is often regarded as the principle element for storing signals in a DRAM cell. In general, the higher the storage capacity of a capacitor, the greater the signal storage capacity of the capacitor will be and the lesser the effect of noise will be when data are read out from the capacitor. For example, if the capacitor has a high capacitance, soft errors generated through bombardment of &agr;-particles are greatly reduced.
A DRAM charge storage capacitor consists of a lower electrode, an insulating dielectric layer and an upper electrode. Typically, the electrodes are doped polysilicon layers and the lower electrode of the charge storage capacitor is in contact with the source/drain terminal of a pass FET to form a polysilicon structure having a lower surface. A portion of the lower electrode may extend into an insulation layer. This insulation layer is formed over other portions of the pass FET and a portion of the region close to the DRAM. Although the lower electrode of the capacitor can have a planar surface, a complicated surface profile is usually formed.
To increase the storage capacity of a capacitor, dielectric material is deposited carefully to form a quality dielectric layer in addition to using a dielectric layer having a high dielectric constant. A further increase in storage capacity is achieved by increasing the surface area of the capacitor electrodes. In an era of device miniaturization, the way to maintain a sufficiently large surface area in each capacitor despite the provision of ever-shrinking substrate area is still an important topic of investigation for semiconductor manufacturers.
FIG. 1
is a schematic cross-sectional view showing a conventional stacked type DRAM capacitor structure. As shown in
FIG. 1
, a semiconductor substrate
100
having a metal-oxide-semiconductor (MOS) transistor
102
thereon is provided. The MOS transistor
102
includes a gate
104
and a pair of source/drain terminals
106
. A field oxide layer
107
and a conductive layer
108
are sequentially formed over the semiconductor substrate
100
. An insulation layer
110
is formed over the substrate
100
. The insulation layer
110
is etched to form a contact opening at a designated location above one of the source/drain terminals
106
. A lower electrode
120
, a dielectric layer
130
and an upper electrode
140
are sequentially formed over the contact opening, thereby forming a stacked capacitor structure
150
. The dielectric layer
130
can be a nitride/oxide (NO) composite layer or an oxide
itride/oxide (ONO) composite layer. The lower electrode
120
and the upper electrode
140
can be polysilicon layers. The lower electrode
120
can have an undulating cross-sectional profile to increase surface area of the capacitor
150
. Finally, a metal contact
106
and a passivation layer (not shown in the figure) are formed over the substrate
100
to form a complete DRAM structure.
The aforementioned stacked capacitor is frequently employed to form DRAM units. Although surface morphology of a capacitor is improved by producing various types of undulating profiles, the increase in capacitance is insufficient to compensate for a reduction of size due to miniaturization.
Other methods of increasing the surface area of a capacitor are also developed, including the production of an uneven surface structure such as a crown, a cylinder, a fin, a branch or a cavity. Sometimes, hemispherical silicon grains (HSG) are even grown over these surface structures. However, these structures are formed by undergoing a series of complicated steps, thereby increasing manufacturing difficulties and cost of production.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide an easier method of manufacturing a high-storage-capacity semiconductor capacitor.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of manufacturing a dynamic random access memory (DRAM) capacitor. A semiconductor substrate having a metal-oxide-semiconductor (MOS) transistor thereon is provided. An insulation layer is formed over the semiconductor substrate. A triblock copolymer layer is formed over the insulation layer by performing a spin-coating process. The triblock copolymer layer is patterned and then the triblock copolymer layer is annealed at a low temperature. The annealed triblock copolymer is exposed to ultraviolet rays in an atmosphere containing ozone so that the triblock copolymer is converted into a bicontinuous three-dimensional nanoporous material. The triblock copolymer layer serves as the lower electrode of a capacitor. A dielectric layer is formed over the lower electrode. An upper electrode is formed over the dielectric layer. The upper electrode, the dielectric layer and the lower electrode are sequentially patterned to form the DRAM capacitor.
This invention also provides a lower electrode structure that uses a bicontinuous three-dimensional nanoporous material. The material not only has a high degree of internal regularity, but also has a high degree of convolution. Moreover, the porosity and degree of complexity of the structure is difficult to reproduce by a conventional photolithographic process. Since porous material can increase surface area, a lower electrode made from the bicontinuous three-dimensional nanoporous material has a greater overall surface area than an electrode made from conventional material.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
“Ordered Bicontinuous Nanoporous and Nanorelief Ceramic Films from Self Assembling Polymer Precursers”, Science, vol. 286, pp. 1716-1719, Nov. 26, 1999.*
Chan et al.,Ordered Bicontinuous Nanoporous and Nanorelief Ceramic Films from Self Assembling Polymer Precursors, Science, vol. 286, Nov. 26, 1999, pp. 1716-1719.
J.C. Patents
Taiwan Semiconductor Manufacturing Co. Ltd.
Wojciechowicz Edward
LandOfFree
Method of manufacturing semiconductor capacitor does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of manufacturing semiconductor capacitor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing semiconductor capacitor will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2945063