Electrical computers and digital data processing systems: input/ – Input/output data processing – Peripheral adapting
Reexamination Certificate
1998-12-28
2002-02-12
Lee, Thomas (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Peripheral adapting
C710S100000, C710S112000, C710S120000, C711S117000
Reexamination Certificate
active
06347349
ABSTRACT:
TECHNICAL FIELD
The present invention relates in general to data processing systems, and in particular, to transaction ordering in multiple processor node data processing system architectures.
BACKGROUND INFORMATION
Modem data processing systems incorporate a plurality of processing nodes. Each node may itself include one or more central processing units (“CPU”), system memory, which may itself include cache memory, peripheral devices, and a peripheral host bridge (“PHB”) coupling a system bus to a peripheral bus.
Additionally, modem data processing systems having multiple processors may implement a shared memory environment. In such environments, a processor, or processors, in one node may access the memory in the other nodes. Typical environments for implementing shared memory across multiple nodes are the non-uniform memory access (NUMA) environment and the cache-only memory access (COMA) environment. Additionally, it is desirable in these systems to implement direct memory access (DMA) by devices in each node, to both local memory and remote memory.
The nodes in such a NUMA or COMA system are coupled via a device, referred to as a “fabric,” which mediates the transactions therebetween. Node-node transactions across the fabric, which may include load/store (L/S) operations to I/O devices and DMA peer-to-peer transactions, may give rise to coherency loss, unless the fabric includes a mechanism for transaction ordering. Coherency constraints may be imposed by the architecture of the CPUs in each node, and may also be imposed by the architecture of the buses in each node. Additionally, transaction ordering must be imposed to avoid deadlocks and assuring data in the coherency domain of the system following I/O interrupts. Thus, there is a need in the art for an apparatus and methods for implementing transaction ordering rules across the fabric connecting multiple nodes in a shared memory environment that preserves coherency and avoids transaction deadlocks.
SUMMARY OF THE INVENTION
The aforementioned needs are addressed by the present invention. Accordingly, there is provided, in a first form, a data processing system including a fabric bridge. The fabric bridge is operable for mediating transactions between nodes in the data processing system, the fabric controlling a sequence of transactions between the nodes wherein the fabric bridge determines an ordering of a preceding transaction and a subsequent transaction. The ordering is one of the subsequent transaction may be allowed to bypass, must be allowed to bypass, and must not be allowed to bypass, the preceding transaction, and wherein said sequence of transactions include load/store (L/S) to input/output (I/O) device, and direct memory access (DMA) peer-to-peer transactions.
There is also provided, in a second form, a method of mediating transactions between nodes in a data processing system. The method includes the step of controlling a sequence of transactions between the nodes by determining an ordering of a preceding transaction and a subsequent transaction, the ordering is one of the subsequent transaction may be allowed to bypass, must be allowed to bypass, and must not be allowed to bypass, the preceding transaction, and wherein said sequence of transactions include load/store (L/S) to input/output (I/O) device, and direct memory access (DMA) peer-to-peer transactions.
Additionally, there is provided, in a third form a computer program product operable for storage on program storage media, the program product operable for mediating transactions between nodes in a data processing system. The program product includes programming for controlling a sequence of transactions between the nodes by determining an ordering of a preceding transaction and a subsequent transaction, the ordering being one of the subsequent transaction may be allowed to bypass, must be allowed to bypass, and must not be allowed to bypass, the preceding transaction, and wherein said sequence of transactions include load/store (L/S) to input/output (I/O) device, and direct memory access (DMA) peer-to-peer transactions.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.
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Neal Danny Marvin
Thurber Steven Mark
Elamin Abdelmoniem
International Business Machines Corp.
Lee Thomas
Leeuwen Leslie Van
Newberger Barry S.
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