Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Flip chip
Reexamination Certificate
2000-03-02
2002-11-05
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Flip chip
C257S737000, C257S738000, C257S787000, C257S723000, C438S108000, C438S112000, C438S124000
Reexamination Certificate
active
06476502
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device containing a semiconductor chip connected to connection terminals by a flip-chip bonding method and a manufacturing method thereof.
2. Description of the Background Art
FIG. 14
is a sectional view of a prior art semiconductor device. The prior art semiconductor device shown in
FIG. 14
includes a package
10
made from an insulating resin for forming the external shape, and an insulating substrate
12
provided on one side of the package
10
. A plurality of external electrode terminals
14
arranged in a matrix are provided on a surface of the insulating substrate
12
. Pads for wire bonding (W/B) are also provided on the other surface of the insulating substrate
12
. Hereinafter, the surface of the insulating substrate
12
on which the external electrode terminals
14
are provided is called a “front surface” of the insulating substrate
12
, and the surface of the same on which the pads for W/B are provided is called a “back surface” of the insulating substrate
12
.
A plurality of semiconductor chips, i.e., a lower chip
16
and an upper chip
18
are molded in the package
10
. Each of the lower chip
16
and the upper chip
18
includes a plurality of inner connection terminals on its one surface. Hereinafter, the surface of each chip on which the inner connection terminals are provided is called a “front surface” of the chip, and the other side surface thereof is called a “back surface” of the chip.
The back surface of the lower chip
16
is fixed to the insulating substrate
12
with a die bond resin
20
. The front surface of the lower chip
16
has at its peripheral edge a space in which the plurality of inner connection terminals are arranged, and also has at its central portion a space for mounting the upper chip
18
. The back surface of the upper chip
18
is fixed to the front surface of the lower chip
16
at the central space thereof with the die bond resin
20
. The inner connection terminals of the lower chip
16
and the inner connection terminals of the upper chip
18
are connected to the pads for W/B of the insulating substrate
12
by means of respective inner connection wires
22
for W/B.
In the above-described. prior art semiconductor device, it is required to ensure on the lower chip
16
the space for disposing the inner connection terminals as well as the space for mounting the upper chip
18
. Accordingly, in the structure of the prior art semiconductor device, it was necessary to make the lower chip
16
larger than the upper chip
18
. Limitation that should be satisfied with the lower chip
16
are not only the above-described limitation of the size. Namely, the lower chip
16
should also meet a limitation regarding the layout of the inner connection terminals. For this reason, in general, a semiconductor device containing a plurality of semiconductor chips has been designed with difficulty.
There has been known a flip-chip bonding (FCB) method as the semiconductor chip bonding method in addition to the above-described W/B method. In the FCB method, a plurality of inner connection terminals provided on the surface of a semiconductor chip are bonded to pads provided on a substrate or the like via bumps.
SUMMARY OF THE INVENTION
The present invention has been conceived to solve the previously-mentioned problems, and a first object of the present invention is to connect part or all of a plurality of semiconductor chips contained in a single semiconductor device to connection terminals by making use of the FCB method, thereby eliminating the limitation in terms of the chip size.
A second object of the present invention is to make finer the arrangement pitch of inner connection terminals of a semiconductor chip by enhancing the dimensional accuracy of bumps used for the FCB method.
The above objects of the present invention are achieved by a semiconductor device having a plurality of semiconductor chips including a first semiconductor chip bonded by a flip-chip bonding method. The semiconductor device includes bonding bumps bonded to inner connection terminals formed on the front surface of the first semiconductor chip or metal films for covering the inner connection terminals. The semiconductor device also includes bonding pads bonded to the inner connection terminals of the first semiconductor chip via the bonding bumps. A thermosetting resin film is provided for surrounding the bonding bumps. In the inventive semiconductor device, a non-wetted region in which the bonding bump is not wetted is formed on the inner connection terminal or the metal film.
The above objects of the present invention are also achieved by a method of manufacturing a semiconductor device including a first semiconductor chip bonded by the flip-chip bonding method. In the inventive method, a thermosetting resin film is formed in such a manner as to cover a plurality of bonding pads to be conducted to inner connection terminals of the first semiconductor chip. The first semiconductor chip is set in such a manner that bonding bumps bonded to the inner connection terminals of the first semiconductor chip or metal films for covering the inner connection terminals are in contact with the bonding pads after penetrating the thermosetting resin film. Further, the thermosetting resin film is thermally cured after completion of the setting of the first semiconductor chip. Finally, the bonding bumps are melted after thermal curing of the thermosetting resin film for bonding the bonding bumps to the bonding pads.
Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.
REFERENCES:
patent: 4933744 (1990-06-01), Segawa et al.
patent: 5323060 (1994-06-01), Fogal et al.
patent: 5610442 (1997-03-01), Schneider et al.
patent: 5715144 (1998-02-01), Ameen et al.
patent: 5784264 (1998-07-01), Tanioka
patent: 5866949 (1999-02-01), Scheuller
patent: 5872700 (1999-02-01), Collander
patent: 5880530 (1999-03-01), Mashimoto et al.
patent: 5895976 (1999-04-01), Morrell et al.
patent: 5952725 (1999-09-01), Ball
patent: 5977632 (1999-11-01), Beddingfield
patent: 5977640 (1999-11-01), Bertin et al.
patent: 6229215 (2001-05-01), Egawa
patent: 6239366 (2001-05-01), Hsuan et al.
patent: 0782191 (1997-02-01), None
patent: 6-209071 (1994-07-01), None
patent: 10-256259 (1998-09-01), None
patent: 1997-53159 (1997-07-01), None
patent: 1999-14197 (1999-02-01), None
Kimura Michitaka
Yamada Satoshi
Yasunaga Masatoshi
Loke Steven
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Parekh Nitin
LandOfFree
Semiconductor device and manufacturing method thereof does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device and manufacturing method thereof, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device and manufacturing method thereof will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2944335