Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1999-06-14
2002-10-08
Meyers, Paul R. (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C714S010000
Reexamination Certificate
active
06463488
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an apparatus and method for testing master logic units within a data processing apparatus.
2. Description of the Prior Art
A common technique for testing a logic unit within a data processing apparatus is to stimulate that logic unit's inputs with test data and to capture the outputs via test accesses. These test accesses are seen as normal accesses by the logic unit (often referred to as the “Unit Under Test” (UUT)), the only difference being that the accesses are stimulated and controlled externally via a test interface driver, which is coupled to the data processing apparatus via a dedicated test access port.
This approach works well for UUTs that are designed to be recipients of processing requests rather than initiating such processing requests. Such logic units can be referred to as “slave” logic units, whereas logic units that are designed to initiate processing requests can be referred to as “master” logic units.
When testing master logic units using the above technique, the UUT needs to be reconfigured so that it can act as a recipient of processing requests generated by a test controller. This reconfiguration allows testing of the internal logic of the master logic unit to a certain extent, but requires special logic to be incorporated for test purposes. The special logic is used to drive the internal inputs (that in normal conditions would be provided by the slave that is communicating with the master), and to sample the outputs (that in normal conditions will be destined for the slave that is communicating with the master).
The overhead of this extra test logic is often justified by the intrinsic complexity and size of the master logic unit's internal logic. However, there are a significant number of cases where the small size and complexity of the master logic unit does not justify the comparatively large test logic overhead.
Further, although this extra test logic allows a significant part of the master logic unit's internal logic to be validated, the interface and the associated logic that enables the master logic unit to drive processing requests onto the system bus (ie the logic that enables the master logic unit to act as a “master”) remains untested.
An object of the present invention is to provide a technique which allows more effective testing of a master logic unit within a data processing apparatus.
SUMMARY OF THE INVENTION
Viewed from a first aspect, the present invention provides a data processing apparatus, comprising: one or more master logic units for accessing a bus in order to generate processing requests; a test controller for testing logic units of the data processing apparatus; an arbiter for receiving bus request signals from the test controller and the one or more master logic units, and for applying predetermined priority criteria to control access to the bus by the test controller and the master logic units, the predetermined priority criteria identifying the relative priority of each master logic unit and the test controller; in a normal test mode, the test controller having a higher priority than any of the master logic units to be tested; and in a master test mode, when master functionality of a first master logic unit is to be tested by the test controller, the arbiter being arranged to receive a priority access signal to cause the arbiter to assign the first master logic unit a higher priority than the test controller, in order to allow the first master logic unit to have access to the bus in order to generate a test processing request.
In accordance with the present invention, the data processing apparatus has one or more master logic units which may access a bus in order to generate processing requests, and a test controller for testing logic units of the data processing apparatus. Predetermined priority criteria are provided identifying the relative priority of each master logic unit and the test controller, and an arbiter is provided for applying the predetermined priority criteria in order to determine which of the one or more master logic units or the test controller should have access to the bus at any particular moment in time. Indeed, the test controller is a master logic unit itself, and the arbiter merely treats the test controller as one of the master logic units. Only one master logic unit can access the bus at any particular moment in time, and the arbiter ensures that, of all the units requesting access to the bus, the unit having the highest priority (whether it be the test controller or one of the master logic units) is granted access to the bus.
In a normal test mode, the test controller has a higher priority than any of the master logic units being tested, and hence the master logic units being tested cannot be granted access to the bus whilst the test controller is performing testing. Hence, in normal test mode, the master logic unit under test is unable to drive processing requests onto the bus, and so the interface functionality of the master logic unit cannot be tested. However, in accordance with the present invention, a master test mode is provided, in which when master functionality of a first master logic unit is to be tested by the test controller, the arbiter is arranged to receive a priority access signal to cause the arbiter to assign the first master logic unit a higher priority than the test controller. This allows the first master logic unit to have access to the bus in order to generate a test processing request, even though the test controller may still be requesting access to the bus. By this approach, the master logic unit being tested is allowed to fully exercise its master functionality by allowing that master logic unit to drive processing requests onto the bus in a controlled manner.
Hence, it can be seen that the technique of the present invention enables the interface logic of the master logic unit to be tested, this also inherently causing parts of the core logic of the master logic unit that interact with the interface logic to be tested. This enables the complexity and size of the actual test logic provided within the master logic unit to test the core logic to be reduced over that required by the previously discussed prior art technique.
In preferred embodiments, upon completion of the test processing request, the priority access signal is deactivated, so that subsequent access to the bus is controlled by the predetermined priority criteria. Clearly, the exact moment in time at which the priority access signal is deactivated will depend on the manner in which the arbiter grants access to the bus, and hence the priority access signal can be deactivated at any appropriate point following completion of the test processing request by the first master logic unit. Further, in alternative embodiments, as will be discussed later, the priority access signal can be continuously asserted throughout a sequence of test processing requests, and then deactivated once the entire sequence of test processing requests has been completed.
Preferably, upon completion of the test processing request, the test controller is arranged to access the results of the test processing request performed by the first master logic unit. Since upon completion of the test processing request, the priority access signal is typically deactivated, thereby causing the arbiter to once again control access to the bus in accordance with the predetermined priority criteria, this enables the test controller to read the appropriate registers or memory locations in order to retrieve the results of the test processing request, and thereby determine whether the master logic unit being tested has functioned correctly.
The priority access signal may itself be a bus request signal issued instead of, or in addition to, the first master logic unit's normal bus request signal when the master logic unit is being tested in the master test mode. However, in preferred embodiments, the priority access signal comprises a priority enable signal
ARM Limited
Meyers Paul R.
Nixon & Vanderhye P.C.
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