Selectively powering X Y organized memory banks

Details Selectively powering X Y organized memory banks Selectively powering X Y organized memory banks

1999-05-19

2002-08-27

Kim, Matthew (Department: 2186)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

C711S205000, C711S005000, C365S230030

Reexamination Certificate

active

06442667

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The technical field of this invention is low power computer memory and particularly selectively powered cache memory.
BACKGROUND OF THE INVENTION
The microprocessors used in current personal computers operate upon data at very high speeds. This is particularly true for superscalar microprocessors that can operate on more than one instruction at a time. It is not economically feasible to construct the entire computer memory system to operate at the same rate as the microprocessor. Further, it is not necessary to construct such a memory system. Microprocessors employ data or instruction caches based upon an assumption of locality. Having once referenced particular data or a particular instruction from main memory, it is normally the case that nearby data or instructions will be referenced again in the near future. It is feasible to construct a small and fast memory to temporarily store such data or instructions. This small fast memory is called a cache. It is typical to recall data from the main memory in minimum sizes larger than the minimum addressable memory size. Such memory recalls may be via a data bus wider than the minimum addressable data size or via bursts of plural memory accesses or both. Such recall of adjacent data also serves the locality assumption by recalling from nearby addresses that are likely to be referenced in the near future. Memory caches store their data with an indication of the corresponding main memory address.
Each memory reference by the microprocessor is tested against these cache address indications to determine if the referenced address is cached. If the referenced address is stored in the cache, called a cache hit, then the memory access takes place within the cache rather than the main memory. Since memory access to the cache is faster than access to the main memory, each cache hit represents a gain in memory access speed. Note that such memory accesses may be made for both reads of the memory and writes to the memory. If the referenced address is not stored in the cache, called a cache miss, then the main memory must be accessed. In a read access, the microprocessor operation unit needing the data must stall until the data is returned from the slower main memory. When recalled, this main memory data is both supplied to the requesting microprocessor operation unit and stored in the cache.
With the need for larger cache memories that operate a higher speeds, power consumption becomes a problem. In CMOS circuits the electric power consumed is directly proportional to both the operational speed and the number of circuits. Accordingly, there is a need in the art for additional techniques for reducing electrical power consumption of cache memories.
SUMMARY OF THE INVENTION
This invention is memory system including plural memory banks. The memory banks are logically disposed into an array of X rows and Y columns. A first decoder selectively powers one of the Y columns corresponding to a first predetermined set of address bits. A second decoder selectively powers one of the X rows corresponding to a second predetermined set of address bits. A first plurality of multiplexers connected to the data busses of memory banks of a corresponding column selects the data bus of said selected row. A second multiplexer connected to each of the first multiplexers selects one of the columns. Thus one of the plural memory banks is powered and selected for memory access corresponding to the first and second predetermined sets of bits of the received address.
This memory system is preferably a cache memory. The cache memory also includes a further column of X rows of memory banks storing cache addresses and cache control data including at least a cache valid tag. A third multiplexer connected to the data busses of the further column selects one row corresponding to the second predetermined set of address bits. A valid and equal unit indicates whether data received from the third multiplexer includes a cache valid tag indicating a valid address and a cache address matching the received address. This indicates a cache hit.
The memory system preferably includes a table look aside buffer translating a predetermined number of most significant address bits from a virtual address to a physical address. A third predetermined set of address bits including at least one translated bit and one untranslated bit addresses the selected row of the further column of memory banks. These third predetermined set of address bits are preferably translated by a micro table look aside buffer.


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OPTI Data Sheet 82C802G-0.1, pp. 19-22.

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