Diagnostic procedures in an integrated circuit device

Details Diagnostic procedures in an integrated circuit device Diagnostic procedures in an integrated circuit device

1997-12-19

2002-08-06

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C714S038110, C714S039000

Reexamination Certificate

active

06430727

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to diagnostic procedures in an integrated circuit device, and particularly to interrupting normal operation of a CPU particularly to allow diagnostic procedures to be effected.
BACKGROUND OF THE INVENTION
There are many designs and architectures for CPUs integrated onto a silicon chip, where the CPU may represent the majority of the silicon area or just some fraction of it, and where the CPU executes instructions which are stored in on-chip or off-chip memory. Typically such a CPU contains a register which acts as the pointer to, or memory address of, an instruction for execution which may be known variously as Instruction Pointer (Iptr), Program Counter (PC) and others. There may be several registers containing various versions of the Instruction Pointer such as: the pointer to the instruction currently executing, the pointer to the next instruction to be executed, the pointer to the next instruction to be fetched from memory, etc.
According to the various possible architectures, the task of fetching instructions from memory may be performed by a distinguishable instruction fetch unit. Further variations include letting such an instruction fetch unit access memory independent from normal CPU data accesses, inserting a cache, or inserting separate instruction and data caches between the CPU and main memory.
Knowledge of the value of the Instruction Pointer register is of particular importance when performing diagnostic functions on software which is running on a CPU. In the simplest case, the value of the Instruction Pointer can be deduced by observing the memory address value on an external memory bus. In more complex examples however, the value of the Iptr is hidden within the depths of the CPU.
Another important feature for software diagnostics is the ability to stop the CPU, or take some other action, when it reaches a particular instruction. This is commonly known as breakpointing. There exist CPUs integrated onto a silicon chip which include one or more registers tightly coupled with the CPU which act as breakpoint registers, where each such a register contains the breakpoint value. These registers may be loaded via the CPU itself, or may be loaded via other means such as a scan chain. When the Iptr matches one of the breakpoint register values the CPU is stopped.
In one known scheme, when the Iptr matches one of the breakpoint register values the CPU is stopped. This solution needs the hardware present in or very closely associated with the CPU and so it cannot easily be removed for production versions. It needs a mechanism for loading any breakpoint registers which is either intrusive if this has to be done via the CPU itself or requires other hardware support such as additional external pins. The situation is complicated when instructions can be fetched but not executed because of an interrupt at the same instance as the CPU was about to execute the breakpointed instruction. Furthermore such a mechanism can only work successfully if the CPU can stop safely at the breakpointed instruction. UK Patent Application No. 9626401.5 discloses an advantageous improved breakpointing scheme incorporating breakpoint registers which overcomes these problems.
The provision of breakpoint registers according to known schemes provide the ability to set one or more “individual” breakpoints, but present a problem to the user if more than the implemented number of breakpoints is desired, or if the user wishes to achieve the breakpoint function when the CPU attempts to execute an instruction anywhere within a “range” of possible instruction addresses.
Existing CPUs often provide a mechanism for executing one instruction at a time, so called single stepping. This involves special logic within the CPU and once activated, the CPU is committed to single stepping and could not, for instance, continue handling an interrupt which has priority over the process being single stepped.
Often a requirement from the user point of view is to single step not one CPU instruction, but one high level instruction which is mapped onto a sequence of CPU instructions. Existing implementations achieve this by single stepping through each of the CPU instructions within a high level instruction and hiding this from the user. The intrusion caused by this may preclude its use in some applications.
It is an object of the present invention to provide an improved breakpointing system in which breakpointing is initiated in response to the instruction pointer having a value within a range.
SUMMARY OF THE INVENTION
According to present invention there is provided a single chip integrated circuit device comprising:
an on-chip CPU comprising fetch and execute circuitry for fetching and executing instructions from a memory, and an address store register for holding an address in memory of a next instruction to be executed;
a bus connected to the CPU for permitting the CPU to access said memory;
a breakpoint range unit having first and second breakpoint registers for holding respectively lower and upper breakpoint addresses between which normal operation of the CPU is to be interrupted for diagnostic purposes, the breakpoint range unit further having comparison logic operative to compare the contents of the address store register with each of the lower and upper breakpoint addresses and to issue a breakpoint signal when the address held in the address store is equal to the lower breakpoint address or between the lower and upper breakpoint addresses;
on-chip control logic connected to receive the breakpoint signal and arranged to interrupt the normal operation of the CPU when the breakpoint signal is received.
Thus, a breakpoint range unit is provided on the chip which contains range comparison logic. The breakpoint range unit may be provided within the CPU itself, or external to the CPU. The breakpoint range logic incorporates techniques to compensate for the considerable increase in delay involved in a greater than or less than comparison over the delay involved in an equivalence comparison.
The breakpoint range unit operates in a non-intrusive manner up until a breakpoint range match occurs. That is, up until a breakpoint match occurs, the loading of the breakpoint registers, and the continuous monitoring of the instruction pointer for a match does not interfere with, or affect the performance of the CPU or other on-chip functionality.
The unit may also facilitate single stepping within or outside a range of instructions and therefore may implement single stepping of one high level instruction.
The breakpoint range unit may further comprise circuitry for inhibiting generation of the breakpoint signal for said next instruction on resumption of normal operation of the CPU after it has been interrupted.
The breakpoint signal can cause the CPU to fetch and execute a, sequence of instructions (so-called “trap instructions”) in place of the next instruction which the CPU would normally have executed. Alternatively, the breakpoint signal can prevent the CPU from any further execution of instructions (STALL AT INTERRUPT POINT) while a diagnostic procedure takes place.
The on-chip control logic can be provided within the CPU itself or in close association with it and this implements the function of stopping or taking some other special action when the CPU would have executed an instruction defined by a breakpoint address or breakpoint address range. One particular embodiment is for the special action to be that the CPU takes a trap. Other implementations may implement a stall, halt, stop, non-maskable interrupt or other appropriate action.
The described breakpoint range unit supports single stepping restricted to within or outside the specified range. This extends to supporting interrupts, provided the interrupt routines are outside the specified range. Furthermore, the interrupt latency is not affected by the breakpoint range unit.
The comparison logic preferably comprises comparator circuitry for performing comparisons of the address held in the address register as less than the upper

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