Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2001-04-10
2002-02-19
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S189070, C365S227000
Reexamination Certificate
active
06349068
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a dynamic semiconductor memory device which requires periodic refreshing to retain memory cell contents.
2. Description of the Related Art
With advances in semiconductor manufacturing technology, the packing density and storage capacity of dynamic semiconductor memory devices such as DRAMs (Dynamic Random Access Memories) have been increasing in recent years. In such semiconductor memory devices, a refresh operation in active mode is performed based on an externally applied refresh command, while a refresh operation in power down mode is performed by generating a clock using an oscillator or the like internal to the device, and the addresses of the memory cells to be refreshed are automatically generated by a refresh address counter incorporated in the device.
These prior art DRAMs (or SDRAMS: Synchronous DRAMs) have been configured to refresh all the memory cells in the refresh operation, whether the device is in the active mode or in the power down mode.
However, there are some applications in which the amount of information handled at a time is large but the amount of information that must be retained continuously is small, and consequently, there are many cases in which the data only in selected memory cells in the DRAM need to retained when in the power down state.
Specifically, in battery powered portable terminals (for example, portable telephones), in many cases, if only part of the data in the power-on state can be retained, all the other information need not be retained when in the power down state. However, since the prior art dynamic semiconductor memory device is configured to refresh all the memory cells in the DRAM, it has been difficult to further reduce the power consumption in the power down mode. The need for reducing the power consumption is demanded not only for battery powered portable terminals but also for various other appliances that use dynamic semiconductor memory devices.
The prior art and its associated problem will be described later, in detail, with reference to accompanying drawings.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor memory device that reduces its power consumption in refresh operation and drastically cuts its power consumption in power down mode by refreshing necessary areas only.
According to the present invention, there is provided a semiconductor memory device refreshing memory cells to retain data, comprising a first refresh mode for refreshing all of the memory cells; and a second refresh mode for refreshing a part of the memory cells.
The semiconductor memory device may further comprise a refresh address register for storing address information designating the memory cells to be refreshed in the second refresh mode. The refresh address register may be provided as part of a mode register.
The semiconductor memory device may further comprise a refresh address counter for generating a refresh address; and a comparator for comparing the refresh address with the information stored in the refresh address register wherein, in the first refresh mode, refreshing may be performed at each refresh address generated by the refresh address counter and, in the second refresh mode, refreshing may be performed in accordance with the comparison result output from the comparator.
The semiconductor memory device may further comprise a refresh address counter for generating a refresh address, wherein in the first refresh mode, refreshing may be performed at each refresh address generated by the refresh address counter and, in the second refresh mode, a count range within which the refresh address counter generates the refresh address may be limited in accordance with the information stored in the refresh address register.
The information stored in the refresh address register may include a minimum value defining an address range within which refreshing is performed in the second refresh mode. The information stored in the refresh address register may include a maximum value defining an address range within which refreshing is performed in the second refresh mode.
The information stored in the refresh address register may include a minimum value and a maximum value defining an address range within which refreshing is performed in the second refresh mode. The information stored in the refresh address register may include a count of the number of refresh operations required to refresh all of the memory cells designated to be refreshed in the second refresh mode.
The information stored in the refresh address register may include an initial value to be set in the refresh address counter. The initial value to be set in the refresh address counter may be a minimum value or a maximum value defining an address range within which refreshing is performed.
The information stored in the refresh address register may include an initial value to be set in the refresh address counter and a count of the number of refresh operations required to refresh all of the memory cells designated to be refreshed in the second refresh mode. The initial value to be set in the refresh address counter may be a minimum value or a maximum value defining an address range within which refreshing is performed. The semiconductor memory device may further comprise a plurality of memory cell blocks and the information stored in the refresh address register may include address information for selecting a memory cell block to be refreshed in the second refresh mode.
The semiconductor memory device may further comprise a refresh address counter for counting a first refresh address; and a refresh address generator for generating a second refresh address based on at least part of the output of the refresh address counter and on the information stored in the refresh address register, wherein, in the first refresh mode, refreshing may be performed at the first refresh address and, in the second refresh mode, refreshing may be performed at the second refresh address. The refresh address generator may include a selector. The semiconductor memory device may further comprise a plurality of memory cell blocks and the information stored in the refresh address register may include address information for selecting a memory cell block to be refreshed in the second refresh mode.
In the first refresh mode, refreshing may be performed in synchronism with an external timing signal, and in the second refresh mode, refreshing may be performed in synchronism with an internally generated clock. The frequency of refresh operation in the second refresh mode may be varied in accordance with the number of memory cells designated by the information stored in the refresh address register as the memory cells to be refreshed. The second refresh mode may be a mode for performing self refresh on memory cells when in a power down state.
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Matsuzaki Yasurou
Takemae Yoshihiro
Arent Fox Kintner & Plotkin & Kahn, PLLC
Elms Richard
Fujitsu Limited
Nguyen Hien
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