Non-volatile semiconductor memory device

Details Non-volatile semiconductor memory device Non-volatile semiconductor memory device

2000-04-11

2002-02-19

Chaudhuri, Olik (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S315000, C257S318000

Reexamination Certificate

active

06348710

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, and more particularly to a non-volatile semiconductor memory device which can write, erase and read data at a high speed and at a low voltage.
2. Description of the Related Art
With enlargement of an application field such as a portable telephone and digital still camera, an EEPROM (Electrically Erasable and Programmable Read Only Memory) has rapidly come into wide use. The EEPROM which permits electrical simultaneous erase of data is called a flash EEPROM.
The EEPROM is a non-volatile semiconductor memory device which stores digital information with two or more values according to whether or not a prescribed quantity of charges is stored and reads the digital information by a change in the conduction of a channel region corresponding to the quantity of charges.
The EEPROM is classified into a stacked-gate type and a split gate type. The split-gate type EEPROM is disclosed in e.g. U.S. Pat. Nos. 5,029,230, 5,045,488 and 5,067,108.
An arrangement of the split-gate type EEPROM cell is shown in
FIGS. 5A and 5B
.
FIG. 5A
is a plan view and
FIG. 5B
is a sectional view taken in line X—X in FIG.
5
A.
As seen from these figures, a drain region
102
and a source region
103
are formed on a P-type semiconductor substrate
101
by a prescribed interval spaced apart from each other. A channel region
104
is formed therebetween. A floating gate
106
is formed on a gate insulating film
105
over a region extending from a part of the channel region
104
to a part of the source region
103
. A thick oxide film
107
(hereinafter referred to as “minilocos”) formed by selective oxidation is provided on the floating gate
106
.
A tunnel oxide film
108
is formed to cover the side of the floating gate
106
and a part of the minilocos
107
. A control gate
109
is formed from on the tunnel oxide film and a part of the channel region
104
to on a part of the drain region
102
. On both sides of the EEPROM cell, element isolation oxide films
110
are formed so that it is electrically isolated from adjacent cells.
Now referring to
FIGS. 6A-6C
, an explanation will be given of the operation of the split-gate type EEPROM.
First, in write of data, as seen from
FIG. 6A
, prescribed voltages (e.g. 2 V for the control gate
109
and 10 V for the source region) are applied to the control gate
109
and source region
103
) so that a current flows through the channel region
104
. Thus, channel hot electrons (CHE's) are injected into and stored in the floating gate
106
. The capacitance coupling ratio between the control gate
109
and the floating gate
106
is as low as about 0.2 so that the voltage applied to the source region
103
boosts the potential of the floating gate
106
to promote the injection of CHE's.
On the other hand, in erasure of data, as seen from
FIG. 6B
, with the drain region
102
and source region
103
connected to ground, a prescribed voltage (e.g. 13 V) is applied to the control gate
109
so that the electrons stored in the floating gate
106
are extracted as a Fowler-Nordheim tunneling current (FN tunnelling current) through the tunneling oxide film
108
to the control gate
109
.
Further, in read of data, as shown in
FIG. 6C
, a prescribed voltage (e.g. 2 V) is applied to the control gate
109
and drain region
102
. Then, a channel current corresponding to the quantity of charges stored in the floating gate
106
flows. By sensing the current, the data can be read.
The conventional split-gate type EEPROM described above has the following defects.
In the split-gate type EEPROM, a high electric field is produced in a gap between the control gate
109
and floating gate
106
so that the CHE's are accelerated. This provides an advantage of a short programming time (time required to write data). However, this provides a disadvantage requiring a high voltage for the write and erasure of data.
On the other hand, in a stacked gate type EEPROM in which a control gate is formed on and in alignment with the floating gate, generally, write of data is made by CHE tunneling or FN tunneling, and erasure of data is made by the FN tunneling from the floating gate to the source region. However, this provides a disadvantage of a long programming time.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a non-volatile semiconductor memory device which can write and erase data at a high speed using a low voltage.
Each aspect of the invention described below is separately illustrative of the various embodiments of the invention and is not intended to be restrictive of the broad invention.
In order to attain the above object, in accordance with the first aspect of the invention, there is a non-volatile semiconductor memory device comprising:
a drain region and a source region each formed of a semiconductor layer having a second conduction type which are formed apart from each other on a semiconductor substrate having a first conduction type;
a floating gate formed on a first insulating film over the semiconductor substrate between the drain region and the source region;
a channel region formed in a surface of the semiconductor substrate between one end of the floating gate and the drain region;
a control gate formed on an upper face and side face of the floating gate and the channel over a second insulating film; and
a semiconductor layer having the second conduction type enlarged from the source region to beneath the floating gate.
In accordance with this configuration, since the semiconductor layer having the second conduction type enlarged to beneath the floating gate is formed, a facing area between the source region and floating gate is increased. Therefore, the FN tunneling current flowing through the first insulating film is increased. As a result, write and erasure of data can be made within a short time.
In accordance with the second aspect of the invention, the non-volatile semiconductor memory device according to the first aspect is characterized in that the semiconductor layer having the second conduction type is a region enlarged from the source region to the drain side direction of the floating gate in the surface of the channel region.
In this configuration, the semiconductor layer having the second conduction type is enlarged from the source region to the drain side of the floating gate. Therefore, a facing area between the semiconductor layer and the floating gate can be maximized so that write and erasure of data can be made within a short time.
In accordance with the third aspect of the invention, the non-volatile semiconductor memory device according to the first aspect is characterized in that the semiconductor layer having the second conduction type is a region formed from the source region to reach the vicinity of the end of the floating gate on its drain side. In this configuration, since drain diffusion is made to reach the end position of the channel region beneath the floating gate semiconductor layer having the second conduction type, the facing area between the semiconductor layer and the floating gate can be maximized so that write and erasure of data can be made within a short time.
In accordance with the fourth aspect of the invention, the non-volatile semiconductor memory device according to the first invention is characterized in that the semiconductor layer having the second conduction type is a highly doped impurity region formed so as to generate tunneling between the semiconductor layer and the floating gate during write of data.
In accordance with the fifth aspect of the invention, the non-volatile semiconductor memory device according to any one of the first to the fourth aspect is characterized in that it further comprises a semiconductor layer having the first conduction type formed in the channel region.
In this configuration, although a short channel effect may occur because the channel length is shortened due to the provision of the semiconductor layer having the

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