Semiconductor circuit device with reduced power consumption...

Details Semiconductor circuit device with reduced power consumption... Semiconductor circuit device with reduced power consumption...

2000-03-14

2002-08-13

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S230060

Reexamination Certificate

active

06434075

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor circuit devices, and more particularly, to a semiconductor memory device having a normal operation mode and a self refresh mode.
2. Description of the Background Art
FIG. 39
is a circuit diagram showing a partial structure of a conventional dynamic random access memory (referred to as DRAM hereinafter). Referring to
FIG. 39
, this DRAM includes a sense amplifier of a P channel sense amplifier
36
and an N channel sense amplifier
44
, a pair of bit lines BL and /BL arranged at one side of the sense amplifier, another pair of bit lines BL and /BL arranged at the other side of the sense amplifier, a switch circuit
56
responsive to a bit line select signal BLI
1
for connecting one of the pairs of bit lines BL and /BL to the sense amplifier, and a switch circuit
62
responsive to a bit line select signal BLI
2
for connecting the other pair of bit lines BL and /BL to the sense amplifier.
More specifically, this DRAM employs a shared sense amplifier method. This sense amplifier selects one of the two pairs of bit lines BL and /BL disposed at either side to amplify the potential difference generated between the selected pair of bit lines BL and /BL.
FIG. 40
is a timing chart indicating an operation of the shared sense amplifier of FIG.
39
. The potential is plotted along the ordinate, and time is plotted along the abscissa. As shown in
FIG. 40
, bit line pair BL and /BL is initially precharged to a level of an intermediate potential of (½) Vcc by a bit line equalize/precharge circuit
68
, and a boosted power supply potential Vpp higher than a power supply potential Vcc is supplied to switch circuits
56
and
62
as bit line select signals BLI
1
and BLI
2
, respectively. Accordingly, the pairs of bit lines BL and /BL at opposite sides are connected to the sense amplifier.
When a memory block B
1
, for example, is selected, only the potential of bit line select signal BLI
2
falls from the level of boosted potential Vpp to ground potential GND. As a result, bit line pair BL, /BL in memory block B
2
is disconnected from the sense amplifier, and only bit line pair BL and /BL in memory block B
1
is connected to the sense amplifier.
When the potential of a word line WL rises from the level of ground potential GND to boosted power supply potential Vpp, charge flows from a memory cell
30
connected to that word line WL towards bit line BL, whereby difference in potential occurs between one bit line BL and the other bit line /BL. Here, the potential of bit line BL is pulled up to the level of power supply potential Vcc by P channel sense amplifier
36
, and the potential of bit line /BL is pulled down to the level of ground potential GND by N channel sense amplifier
44
.
In a normal operation mode of a DRAM, bit line select signal BL
1
is maintained at the level of boosted power supply potential Vpp until the potentials of bit lines BL and /BL reach the level of power supply potential Vcc and ground potential GND, respectively. Therefore, bit line pair BL and /BL is continuously connected to the sense amplifier until amplification of that bit line pair is completed. This operation of a shared sense amplifier is carried out, not only in a normal operation mode, but also in a self refresh mode.
FIG. 41
is a circuit diagram showing a structure of a conventional internal voltage-down circuit used in a DRAM. Referring to
FIG. 41
, the internal voltage-down circuit includes a reference potential generation circuit
182
for generating a constant reference potential Vref
1
, a voltage-down converter
164
that is always activated, and a voltage-down converter
190
that is selectively activated. In a standby mode, only voltage-down converter
164
of a low current supply capability operates. In an active mode, voltage-down converter
190
of a great current supply capability operates in addition to voltage-down converter
164
. More specifically, when internal circuit
180
is activated in response to an internal row address strobe signal RASI, a comparator circuit
192
is also activated in response to internal row address strobe signal RASI. Therefore, the internal voltage-down circuit can supply a current of an amount greater than that of a standby state to internal circuit
180
.
In a conventional internal voltage-down circuit, voltage-down converter
190
of a great current supply capability is activated in response to internal row address strobe signal RASI even in a self refresh mode as in a normal operation mode.
Although high speed of a level identical to that of a normal operation mode is not required in a self refresh mode, the operation of the shared sense amplifier in a self refresh mode is identical to that of a normal operation mode as shown in
FIGS. 39 and 40
. This means that a great amount of through current is conducted in the sense amplifier during an amplify operation of a bit line pair that is as much as in a normal operation mode even in a self refresh mode. Therefore, there is a problem that a great amount of power is consumed in a self refresh mode.
Furthermore, in a self refresh mode, the conventional internal voltage-down circuit of
FIG. 41
has the voltage-down converter of a great current supply capability activated in response to internal row address strobe signal RASI as in a normal operation mode. Therefore, similar to a normal operation mode, a great amount of current is consumed even in a self refresh mode.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor memory device that can have power consumption reduced in a special operation mode in which the operation rate is lower than that of a normal operation mode.
Another object of the present invention is to provide a semiconductor circuit device that can have power consumption reduced in a special operation mode in which the operating rate is lower than that of a normal operation mode.
According to an aspect of the present invention, a semiconductor memory device with a normal operation mode and a special operation mode in which the operation rate is lower than that of the normal operation mode includes first and second sense nodes, a sense amplifier, first and second bit line pairs, a plurality of word lines, a row decoder, first and second switch elements, and a control circuit. The sense amplifier is connected to the first and second sense nodes, and amplifies the potential difference generated between the first and second sense nodes. The first bit line pair is arranged at one side of the sense amplifier. The second bit line pair is arranged at the other side of the sense amplifier. The plurality of word lines cross the first and second bit line pairs. The row decoder responds to a row address signal to selectively activate a word line. The first switch element is connected between the first and second sense nodes and the first bit line pair. The second switch element is connected between the first and second sense nodes and the second bit line pair. The control circuit controls the first and second switch elements so as to connect one of the first and second bit line pairs to the sense amplifier in a normal operation mode. In a special operation mode, the control circuit controls the first and second switch elements so that one of the first and second bit line pairs is connected to the sense amplifier, the connected bit line pair is disconnected from the sense amplifier after data is read out therefrom, and the disconnected bit line pair is connected to the sense amplifier again after the sense amplifier is activated.
In a special operation mode, preferably in a self refresh mode, a bit line pair is disconnected from the sense amplifier after data is read out thereto, followed by activation of the sense amplifier. Therefore, the potential difference between the first and second sense nodes is amplified speedily. The through current flowing across the sense amplifier in a special operation mode is smaller than that of a normal operation mode. As

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