Sense amplifier for content addressable memory

Details Sense amplifier for content addressable memory Sense amplifier for content addressable memory

2001-05-24

2002-08-27

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Associative memories

Ferroelectric cell

C365S207000, C365S210130

Reexamination Certificate

active

06442054

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a sense amplifier for use in a content addressable memory (CAM) array.
RELATED ART
A compare operation within a CAM array is typically performed by charging a large number of match lines to a V
DD
supply voltage. If a match condition exists on a particular match line, the match line will remain charged at the V
DD
supply voltage. If no match condition exists on a particular match line, then this match line is pulled down to the V
SS
supply voltage (i.e., ground). Typically, many non-match conditions will exist for each compare operation. Thus, each compare operation consists of charging and discharging many match lines across the full V
DD
supply voltage. As a result, a conventional CAM array consumes a large amount of power. In general, the match lines are subjected to a relatively large signal swing in order to allow the state of the match signal to be accurately sensed.
It would therefore be desirable to have an improved sense amplifier that is able to sense smaller match line signal swings.
SUMMARY
Accordingly, the present invention provides a sense amplifier that operates in response to a voltage swing as small as the difference between two transistor threshold voltages.
In accordance with one embodiment, a sense amplifier includes a first transistor that is used to pre-charge a match line of a CAM array. The first transistor is coupled between the V
DD
supply terminal and the match line. During the pre-charge operation, the gate of the first transistor is coupled to receive a reference voltage V
REF
. As a result, the match line is pre-charged to a voltage equal to V
REF
minus V
T1
, where V
T1
is the threshold voltage of the first transistor. The reference voltage V
REF
is selected to be less than the V
DD
supply voltage in order to achieve power savings.
The sense amplifier also includes a storage node that is pre-charged to the V
DD
supply voltage. The state of the storage node is used to determine whether a match or non-match condition exists on the match line during a compare operation.
A second transistor is coupled between the match line and the storage node of the sense amplifier. The gate of the second transistor is coupled to a dummy line of the CAM array. The dummy line is pre-charged to a voltage equal to the reference voltage V
REF
. As a result, the gate-to-source voltage V
GS
of the second transistor is equal to V
T1
(i.e., or the difference between the gate voltage (V
REF
) and the match line voltage (V
REF
−V
T1
)). The second transistor is designed to have a second threshold voltage V
T2
, which is greater than the threshold voltage of the first transistor, V
T1
. As a result, the second transistor is initially turned off.
During a compare operation, a row of CAM cells coupled to the match line will exhibit a match condition or a non-match condition. If a match condition exists, the match line remains at a voltage of V
REF
−V
T1
. The second transistor remains off under these conditions, thereby allowing the storage node to remain at a logic high state.
If a non-match condition exists, the match line is pulled down toward ground. As soon as the match line is pulled down to a voltage equal to V
REF
minus V
T2
, the second transistor is turned on, thereby pulling down the storage node to a logic low state. Note that the voltage swing required by the sense amplifier is equal to the difference between the first and second threshold voltages (i.e., V
T2
−V
T1
).
In one variation, the sense amplifier is expanded such that a second match line is coupled to the storage node in the same manner as the first match line. In this case, the two match lines correspond with a single row of the CAM array.
In accordance with another aspect of the present invention, a current mirror circuit is coupled to the storage node, thereby supplying a small constant current to the storage node. This constant current helps to maintain the logic high state of the storage node during non-match conditions.
The present invention will be more fully understood in view of the following description and drawings.


REFERENCES:
patent: 6307797 (2001-10-01), Fournez et al.
patent: 6307798 (2001-10-01), Ahmed et al.

Affiliated with

Also associated with

Rating

Sense amplifier for content addressable memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Sense amplifier for content addressable memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Sense amplifier for content addressable memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2941119