Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-03-01
2002-02-26
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S328000, C257S330000, C257S333000, C257S352000
Reexamination Certificate
active
06351009
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor devices and, more particularly, to an MOS-gated device and a process for forming same.
BACKGROUND OF THE INVENTION
An MOS transistor that includes a trench gate structure offers important advantages over a planar transistor for high current, low voltage switching applications. In the latter configuration, constriction occurs at high current flows, an effect that places substantial constraints on the design of a transistor intended for operation under such conditions.
A trench gate of a DMOS device typically includes a trench extending from the source to the drain and having sidewalls and a floor that are each lined with a layer of thermally grown silicon dioxide. The lined trench is filled with doped polysilicon. The structure of the trench gate allows less constricted current flow and, consequently, provides lower values of specific on-resistance. Furthermore, the trench gate makes possible a decreased cell pitch in an MOS channel extending along the vertical sidewalls of the trench from the bottom of the source across the body of the transistor to the drain below. Channel density is thereby increased, which reduces the contribution of the channel to on-resistance. The structure and performance of trench DMOS transistors are discussed in Bulucea and Rossen, “Trench DMOS Transistor Technology for High-Current (100 A Range) Switching,” in
Solid
-
State Electronics,
1991, Vol. 34, No. 5, pp 493-507, the disclosure of which is incorporated herein by reference. In addition to their utility in DMOS devices, trench gates are also advantageously employed in insulated gate bipolar transistors (IGBTs), MOS-controlled thyristors (MCTs), and other MOS-gated devices.
FIG. 1
schematically depicts the cross-section of a trench MOS gate device
100
of the prior art. Although
FIG. 1
shows only one MOSFET, a typical device currently employed in the industry consists of an array of MOSFETs arranged in various cellular or stripe layouts.
Device
100
includes a doped (depicted as N+) substrate
101
on which is grown a doped epitaxial layer
102
. Epitaxial layer
102
includes drain region
103
, heavily doped (P+) body regions
104
, and P-wells
105
. Abutting body regions in epitaxial layer
103
are heavily doped (N+) source regions
106
, which are separated from each other by a gate trench
107
that has dielectric sidewalls
108
and floor
109
. Gate trench
107
is substantially filled with gate semiconductor material
110
. Because the source regions
106
and gate semiconductor material
110
have to be electrically isolated for device
100
to function, they are covered by a dielectric layer
111
. Contact openings
112
enable metal
113
to contact body regions
104
and source regions
106
.
Contact openings
112
are formed in dielectric layer
111
, which typically is a deposited layer of oxide, by conventional mask/etch techniques. The size of device
100
depends on the minimum thickness of dielectric needed for isolation (the lateral distance between a source region
106
and gate trench
107
) and on the tolerance capabilities of the mask/etch procedures. The thickness of dielectric layer
111
is determined not only by the minimum required voltage isolation but also on the need to minimize source-to-gate capacitance, which affects device switching speed and switching losses. Switching losses are directly proportional to the capacitance, which is in turn inversely proportional to the dielectric thickness. Therefore there is a typical minimum thickness of about 0.5-0.8 &mgr;m for dielectric layer
111
in prior art device
100
.
As just noted, the required minimum thickness of dielectric layer
111
imposes limitations on the minimum size of device
100
. It would be desirable to be able to reduce the size and improve the efficiency of semiconductor devices. The present invention provides these benefits.
SUMMARY OF THE INVENTION
The present invention is directed to an improved trench MOS-gated device formed on a monocrystalline semiconductor substrate comprising a doped upper layer. The doped upper layer, includes at an upper surface a plurality of heavily doped body regions having a first polarity and overlying a well region and a drain region. The upper layer further includes at its upper surface a plurality of heavily doped source regions that have a second polarity opposite that of the body regions and extend to a selected depth in the upper layer.
A gate trench extends from the upper surface of the upper layer through the well region to the drain region and separates one source region from a second source region. The trench has a floor and sidewalls comprising a layer of dielectric material and contains a conductive gate material filling the trench to a selected level and an isolation layer of dielectric material that overlies the gate material and substantially fills the trench. The upper surface of the overlying layer of dielectric material in the trench is thus substantially coplanar with the upper surface of the upper layer.
Also in accordance with the present invention is a process for forming an improved, high density, self-aligned trench MOS-gated device. A doped upper layer having an upper surface and an underlying drain region is formed on a substrate, and a well region having a first polarity is formed in the upper layer over the drain region. A gate trench mask is formed on the upper surface of the upper layer, and a plurality of gate trenches extending from the upper surface through the well region to the drain region are etched in the upper layer.
Sidewalls and a floor each comprising a dielectric material are formed in each of the gate trenches, which are filled to a selected level with a conductive gate material. The trench mask is removed, and an isolation layer of dielectric material is formed on the top surface of the upper layer and within the gate trench, where it overlies the gate material and substantially fills the trench. The dielectric layer is removed from the top surface of the upper layer; the dielectric layer remaining within the trench has an upper surface that is substantially coplanar with the upper surface of the upper layer.
A plurality of heavily doped body regions having a first polarity are formed at the upper surface of the upper layer. A source mask is formed on the upper surface, and a plurality of heavily doped source regions having a second polarity and extending to a selected depth into the upper layer are formed in the body regions. Following removal of the source mask, a metal contact to said body and source regions is formed over the upper surface of the upper layer.
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Bulucea, Constantin, et al., “Trench DMOS Transistor Technology for High-Current (100 A Range, Switching”,Solid-State Electronics, vol. 34, No. 5, Head Hill Hall, Oxford, GB, pp. 493-507, (May 1991).
Matsumoto, Satoshi, et al., “A High Performance Self-Aligned UMOSFET With a Vertical Trench Contact Structure”,IEEE Transactions on Electron Devices, vol. 41, No. 5, New York, New York, US, pp. 1-5, (May 1994).
International Search Report.
Jonathan Evans, et al., “The Behaviour of Very High Current Density Power MOSFET's”,IEEE Electron Devices Society, pp. 157-160 (May 1996).
Jonathan Evans, et al., The Behavior of Very High Current Density Power MOSFET&apo
Kocon Christopher B.
Zeng Jun
Fairchild Semiconductor Corporation
Jaeckle Fleischmann & Mugel LLP
Lee Eddie
Ortiz Edgardo
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