Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Reexamination Certificate
2001-05-09
2002-06-11
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
C326S095000, C326S098000, C327S208000
Reexamination Certificate
active
06404234
ABSTRACT:
FIELD OF THE INVENTION
The invention relates generally to semiconductor logic devices, and more specifically to domino logic circuitry having a variable virtual ground circuit operable to vary a virtual ground level of a static output circuit stage.
BACKGROUND OF THE INVENTION
Semiconductor operational frequencies are ever increasing, requiring circuitry and processes that support these faster clock rates. Domino circuits have been used in such circuits to speed processing, due to the way in which a domino logic circuit handles data. Domino circuits are often used in critical paths in processors and other digital logic, where low latency is an important design factor. A typical domino logic circuit receives data on a first transition of a clock, and couples a logically derived signal to external circuitry on a next transition of the clock.
A conventional domino circuit includes dynamic circuitry coupled to static gate circuitry. The dynamic circuitry pre-charges an input of the static circuitry high when a clock signal is low, and couples an input data signal to the static circuitry when the clock signal is high. The dynamic circuitry often is n-type metal oxide semiconductor (NMOS) pull-down circuitry, that is operable to pull down the level of a relatively weakly held pre-charged circuit node. The node is then latched in static CMOS circuitry to provide a stable output until the next logical cycle.
But, the speed of such logic is limited by the time it takes to pre-charge the dynamic circuit node that provides the data signal to the static CMOS latch and the output, and by the time it takes to pull down the weakly-held precharged node voltage to provide a low signal level to the static CMOS latch circuitry and to change the state of the output. Simply fabricating a larger keeper circuit will achieve the desired noise immunity, but at a greater delay due to the stronger level keeper circuit that must be overcome in the evaluation phase.
One solution to such problems is to reduce the physical size of the circuit elements and reduce the supply and threshold voltages within the circuit, resulting in physically smaller devices able to change state over a smaller voltage range more quickly. But, the reduced threshold voltages and smaller geometry result in high subthreshold and leakage current in the transistors. Also, the low threshold voltages coupled with faster signal edges and greater noise coupling due to smaller geometry contribute to increasingly substantial noise problems. Some high fan-in gates such as high fan-in dynamic NOR gates are particularly noise prone, and so benefit from a higher threshold voltage. A higher threshold voltage may be used to compensate for higher noise, but a circuit providing a lower threshold voltage with faster operation is desirable in many applications. As lower threshold devices are used, the resulting higher leakage leads to lower noise immunity.
For these reasons and others that will be apparent to those skilled in the art, need exists for a domino logic circuit that is operable at a low threshold voltage yet that retains an adequate noise margin.
REFERENCES:
patent: 4571510 (1986-02-01), Seki et al.
patent: 4697109 (1987-09-01), Honma et al.
patent: 4899066 (1990-02-01), Aikawa et al.
patent: 5115150 (1992-05-01), Ludwig
patent: 5258666 (1993-11-01), Furuki
patent: 5453708 (1995-09-01), Gupta et al.
patent: 5543735 (1996-08-01), Lo
patent: 5568062 (1996-10-01), Kaplinsky
patent: 5661675 (1997-08-01), Chin et al.
patent: 5671151 (1997-09-01), Williams
patent: 5748012 (1998-05-01), Beakes et al.
patent: 5796282 (1998-08-01), Sprague et al.
patent: 5815005 (1998-09-01), Bosshart
patent: 5825208 (1998-10-01), Levy et al.
patent: 5831990 (1998-11-01), Queen et al.
patent: 5852373 (1998-12-01), Chu et al.
patent: 5886540 (1999-03-01), Perez
patent: 5889417 (1999-03-01), Klass et al.
patent: 5892372 (1999-04-01), Ciraula et al.
patent: 5896046 (1999-04-01), Bjorksten et al.
patent: 5896399 (1999-04-01), Lattimore et al.
patent: 5898330 (1999-04-01), Klass
patent: 5917355 (1999-06-01), Klass
patent: 5942917 (1999-08-01), Chappell et al.
patent: 6002272 (1999-12-01), Somasekhar et al.
patent: 6002292 (1999-12-01), Allen et al.
patent: 6049231 (2000-04-01), Bosshart
patent: 6052008 (2000-04-01), Chu et al.
patent: 6060910 (2000-05-01), Inui
patent: 6087855 (2000-07-01), Frederick, Jr. et al.
patent: 6104212 (2000-08-01), Curran
patent: 6108805 (2000-08-01), Rajsuman
patent: 6133759 (2000-10-01), Beck et al.
patent: 6204696 (2001-03-01), Krishnamurthy et al.
patent: 0954101 (1999-03-01), None
patent: 04-239221 (1992-08-01), None
Bryant, R.E., “Graph-Based Algorithms for Boolean Function Manipulation”,IEEE Transactions on Computers, C-35 (8), pp. 677-691, (1986).
Chakradhar, S.T., et al., “An Exact Algorithm for Selecting Partial Scan Flip-Flops”, Proceedings of the 31st Design Automation Conference, San Diego, California, pp. 81-86, (1994).
Chakravarty, S., “On the Complexity of Using BDDs for the Synthesis and Analysis of Boolean Circuits”,27th Annual Allerton Conference on Communication, Control, and Computing, Allerton House, Monticello, Illinois, pp. 730-739, (1989).
Patra, P., et al., “Automated Phase Assignment for the Synthesis of Low Power Domino Circuits”, Proceedings of the 36th ACM/IEEE Conference on Design Automation, pp. 379-384, (1999).
Puri, et al., “Logic Optimization by Output Phase Assignment in Dynamic Logic Synthesis”,International Conference on Computer Aided Design, 7 p., (1996).
Thompson, S., et al., “Dual Threshold Voltages and Substrate Bias: Keys to High Performance, Low Power, 0.1 um Logic Designs”, Symposium on VLSI Technology Digest of Technical Papers, pp. 69-70, (1997).
Hsu Steven K.
Krishnamurthy Ram K.
Mathew Sanu K.
Intel Corporation
Schwegman Lundberg Woessner & Kluth P.A.
Tan Vibol
Tokar Michael
LandOfFree
Variable virtual ground domino logic with leakage control does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Variable virtual ground domino logic with leakage control, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Variable virtual ground domino logic with leakage control will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2940739