Methods for designing standard cell transistor structures

Details Methods for designing standard cell transistor structures Methods for designing standard cell transistor structures

1999-06-22

2002-11-05

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

06477695

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to integrated circuits, and more particularly to methods for sizing layout design geometries of transistor gates to achieve specific optimized performance characteristics.
2. Description of the Related Art
In the design of semiconductor integrated circuits, circuit designers commonly utilize what are known as “standard cells” to achieve a particular circuit response. Standard cells are essentially pre-designed layouts of transistors that are wired to perform a certain type of logical function. By way of example, a company, such as Artisan Components, Inc. of Sunnyvale, Calif., designs standard cell libraries incorporating many different types of standard cells, each for performing a specific type of logical operation or operations. The standard cells of the standard cell library are then used by integrated circuit design engineers in conjunction with modeling software to produce a larger scale circuit design that meets a particular specification.
A popular and most commonly used modeling software is a hardware description language (HDL) named “Verilog” (IEEE Verilog Standard 1364, 1995). Using Verilog, designers are able to describe each component of an integrated circuit in terms of its functional behavior as well as its implementation. Once a circuit design using Verilog is complete, the Verilog code is synthesized to generate what is referred to as a “netlist.” A netlist is essentially a list of “nets,” which specify components (i.e., standard cells) and their interconnections which are designed to meet the circuit design's performance constraints.
The actual placement plan of the standard cells on silicon and the topography of wiring is reserved for a subsequent “layout” stage. In the layout stage, software tool, commonly referred to as “place and route” software, is used to design the actual wiring that will ultimately interconnect the standard cells together. To do this, each standard cell typically has one or more pins for interconnection with pins of other standard cells. The netlist therefore defines the connectivity between pins of the various standard cells of an integrated circuit device.
Although the design of integrated circuits using specialized software has greatly simplified the design process, the ultimate design is only going to perform as well as the individual standard cells. That is, if standard cells are not individually optimized to meet a specific performance characteristic, the designer of the larger integrated circuit design will find it difficult, and many times, impossible to optimize the resulting larger design to meet some pre-set operation or performance characteristic.
To facilitate discussion,
FIG. 1
shows a prior art standard cell
100
having a p-type transistor and an n-type transistor. The standard cell
100
has a cell height (H
cell
) and a cell length (L
cell
). Although standard cells that represent true logical circuits may implement additional transistors and have associated interconnection wiring (not shown) defined, this simplistic transistor level illustration shows how the standard cell
100
is divided in two parts. As is general practice in CMOS design, one part of the standard cell
100
is for p-type transistors
102
and the other part is for n-type transistors
104
. In some situations, standard cell designers designed the gate width “Wp” of the p-type transistor
102
to be equal to the gate width “Wn” of the n-type transistor
104
. A problem with this design is that p-type transistors are generally know to be weaker in driving strength than their n-type transistor counterparts. As a result, when a standard cell is designed having N and P type transistors with equal gate widths, the designer will need more chip space to design additional p-type transistors to meet the desired drive characteristics.
To combat this known problem, designers shifted their efforts in order come up with standard cells, in which, the drive strength of the p-type transistors substantially equaled the drive strength of the n-type transistors. To achieve this “balanced” drive standard cell design, designers increased the size of the p-type transistors such that they were about 2 to 3 times larger in width that the stronger driving n-type transistors (i.e., ratio={Wp/Wn}=2~3). Thus, the simplistic design of
FIG. 1
shows a case in which the p-type transistor has a gate width Wp that is about 2 or 3 times larger than the gate width Wn of the n-type transistor, thus achieving the desired balanced drive.
An undesirable impact of having P and N type transistors of standard cells with balanced drive is, however, that the standard cell is not optimized with transistor speed nor power consumption in mind. As a result, most balanced drive standard cell designs present substantial difficulties (e.g., due to a fixed standard cell delay) to circuit designers that must meet very tight specifications that require minimum delays in order to implement a fast integrated circuit design. Similarly, designers that face particular constraints to reduce power consumption are also currently required to assume a fixed power consumption specification for the particular standard cell and must, if possible, perform other possibly more expensive design modifications to control power consumption.
In view of the foregoing, there is a need for methods for designing standard cell designs that enable precise optimization of transistor delay characteristics. There is also a need for methods for designing standard cell designs that enable precise optimization of transistor power consumption characteristics.
SUMMARY OF THE INVENTION
Broadly speaking, the present invention fills these needs by providing methods for designing standard cell transistors to obtain optimum results in terms of reduced gate delay and power consumption characteristics. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, a computer readable media, a device, or a method. Several embodiments of the present invention are described below.
In one embodiment, a method for designing standard cell transistor layouts is disclosed. The method includes defining a transistor model for a P-type transistor and an N-type transistor of a CMOS standard cell. The method then includes optimizing a ratio between the P-type transistor and the N-type transistor. The ratio is defined by dividing a P-type gate width of the P-type transistor by an N-type gate width of the N-type transistor. The optimizing is performed by substantially minimizing an average delay for the transistor structure. In this embodiment, the CMOS standard cell will define a transistor structure that is implemented to make a logic circuit. The CMOS standard cell is one of a library of standard cells, where each standard cell defines a particular logic circuit.
In yet another embodiment, a method for sizing transistors of a standard cell is disclosed. The method includes defining a transistor structure for the standard cell. The transistor structure defines a logic circuit upon being interconnected using interconnect metallization and conductive vias structures. The method then includes defining a transistor model for a P-type transistor and an N-type transistor of the standard cell. The P-type transistor is oriented on a first side of the standard cell and the N-type transistor is oriented on a second side of the standard cell. The method further includes generating a plurality of ratios between the P-type transistor and the N-type transistor, such that each of the plurality of ratios are derived by dividing a P-type gate width of the P-type transistor by an N-type gate width of the N-type transistor. The method then generates a plurality of average delays for the transistor structure of the standard cell. In this embodiment, each of the generated plurality of average delays is associated with a corresponding one of the plurality of ratios. The method th

Affiliated with

Also associated with

Rating

Methods for designing standard cell transistor structures does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Methods for designing standard cell transistor structures, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods for designing standard cell transistor structures will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2940584