High speed semiconductor memory device capable of changing...

Details High speed semiconductor memory device capable of changing... High speed semiconductor memory device capable of changing...

1999-01-06

2002-02-05

Bragdon, Reginald G. (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S105000, C711S167000

Reexamination Certificate

active

06345334

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device, and more particularly to a high speed semiconductor memory device capable of changing data sequence for burst transmission for high speed data write and read operations.
One of the recent issues is a large difference in high speed performance between the advanced high speed central processing unit (CPU) and the dynamic random access memory (DRAM). In order to solve the above issue, it has been proposed to provide a cache memory between the CPU and the main memory such as the DRAM, so that the CPU is accessible to the cache memory. This cache memory has a smaller capacity than the main memory such as DRAM but is capable of high speed access for high speed data write and read operations. The cache memory has copy data as a part of the data stored in the main memory. These copy data comprise plural data sets, each of which comprises data corresponding to consecutive addresses are stored in individual blocks. The consecutive data sets are individually stored in the cache memory. The CPU has access to the cache memory for reading out the required copy data from the cache memory. If, however, the cache memory does not have the required copy data, the copy of the currently required data stored in the main memory is made in a free memory area of the cache memory, before the CPU may gain a second access to the free memory area of the cache memory for reading out the required copy data. If, however, the cache memory has no free memory area for storing any copy data, then data with a likely small degree of necessity are transferred from the cache memory to the main memory in order to form a free memory area for making copy data of the currently required data in the main memory in the free memory area of the cache memory, before the CPU has access to the cache memory for reading out the required copy data from the cache memory.
It is, therefore, required for the main memory to have a high speed access to the cache memory for high speed writing and reading a data column corresponding to consecutive addresses. Responsive to this requirement, the DRAM has been improved for conducting a burst transmission of data corresponding to consecutive addresses, wherein only a head address is designated for writing and reading operations of this head address data in combination with subsequent data corresponding to the consecutive addresses following the head address in the form of a data column synchronized with an externally supplied reference clock signal. Synchronous DRAM and high speed static random access memory (SRAM) are the conventionally improved main memories capable of burst transmission. A length of the data column for burst transmission is the burst length.
Usually, a general-purpose DRAM which has a first page mode transmits data sequentially so that a datum has been transmitted before a next datum is transmitted. The datum transmission speed of the advanced general-purpose DRAM is only 20 ns at 50 MHz. In the meantime, the synchronous DRAM takes almost the same time to conduct the datum transmission for writing and reading a datum as the advanced general-purpose DRAM. Notwithstanding, the synchronous DRAM is capable of multiplexing internal processings for concurrent writing and reading operations of a set of plural data so as to shorten an apparent data transmission time, so that the data transmission is carried out at an effective transmission speed corresponding to the frequency of the reference clock signal of 100 MHz or higher which is called the burst transmission frequency.
Meanwhile, the pre-fetch system is effective to increase the data input or output speed with multiplication of the internal processings of the main memory. In this pre-fetch system, the memory carries out in parallel the same plural internal processes of the plural data sets. The data input is carried out sequentially, for which reason data sequentially inputted or entered are temporally latched to accumulate the same amount of data as can be processed in the parallel internal processings for carrying out in parallel the same plural internal processes of the plural data sets, wherein the number of data to be temporally latched is equal to the number of the parallel internal processings. The parallel internal processings individually need individual reference clock signals, for which reason there are needed the same number of the reference clock signals as the parallel internal processings.
The above conventional pre-fetch system semiconductor memory device has the following problems. In order to conduct the burst transmission of data per n-byte unit, a less significant bit of the head address and a counted number of the clocks are added to each other for carrying out the write and read operations of the data in n-byte units. In this case, the data to be read out comprise the head address datum and subsequent (n−1)-byte data having the consecutive addresses following the head address. For example, it is now considered that four bytes are read from the n-bytes data D
0
-Dn−1. If D
0
is designated as the head address, then data D
0
-D
3
are read. If D
1
is designated as the head address, then data D
1
-D
4
are read. If D
2
is designated as the head address, then data D
2
-D
5
are read. If Dk is designated as the head address, then data Dk-Dk+3 are read, where k is 0 to n−4.
It is further assumed that a memory cell array for storing data comprises four blocks which are connected to common word lines. In order to read data D
0
-D
3
, it is necessary to designate the same common word line. In order to read data D
1
-D
4
, it is necessary to designate both a first common word line for reading the data D
1
-D
3
and subsequently a second common word line for reading the datum D
4
. Namely, the first common word line commonly connected to memory cells storing the data D
1
-D
3
is activated to read the data D
1
-D
3
before the first common word line enters into an inactivated state and then the second common word line connected to a memory cell storing the datum D
4
is selected and further a bit line connected to that memory cell comes out of the pre-charge state so as to allow a sense amplifier to activate the word line connected to the memory cell storing the datum D
4
for reading the datum D
4
. During the processes for switching the word lines, the CPU contacts the wait processings. The processes for reading the data D
1
-D
4
are more complicated than the process for reading the data D
0
-D
3
. Those descriptions are common and applicable to the writing operations.
The necessary time for writing and reading consecutive data corresponding to the consecutive addresses depends upon whether the common word line connected to the memory cells storing a part of the consecutive data is switched into the different common word line connected to the memory cells storing the remaining part of the consecutive data. If necessary, the necessary time for writing and reading the consecutive data would largely depend upon the necessary time for the above word line switching operations. This makes it difficult to realize the increased high speed performance of the semiconductor memory device.
In the above circumstances, it had been required to develop a novel high speed semiconductor memory device for burst transmission for high speed data write and read operations.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a novel semiconductor memory device free from the above problems.
It is a further object of the present invention to provide a novel high speed semiconductor memory device for burst transmission for high speed data write and read operations.
The present invention provides a method of switching sequences of unit data comprising plural bytes to be consecutively transmitted as a unit for at least one of data write or read operations, wherein, in accordance with a designated address of a memory area, any sequences of the unit data are so switched that a correspond

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