Electrical computers and digital data processing systems: input/ – Input/output data processing – Peripheral configuration
Reexamination Certificate
1999-10-21
2002-08-20
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Peripheral configuration
C710S003000, C710S008000, C710S301000, C710S300000, C361S788000
Reexamination Certificate
active
06438625
ABSTRACT:
The present invention relates generally to digital systems, and particularly to providing contiguous addresses for boards which are plugged into a secondary backplane, which in turn is plugged into a primary backplane.
BACKGROUND OF THE INVENTION
The computer system
100
illustrated in
FIG. 1
includes one or more CPU's
101
, a communications interface
102
, a user interface
107
, and memory
108
. A set of board level subsystems
110
are coupled to the main CPU
101
by the communications interface
102
. The communications interface may include data, address and control busses on a backplane. The memory
108
includes an operating system
103
, a file system
104
, applications programs
105
and a board communications program
106
that handles communications with the board level subsystems
110
.
As shown in
FIG. 2
, the system
100
may be implemented as a set of boards
152
that are plugged into slots
151
on a backplane
153
. A host controller
154
corresponds to the system components shown in
FIG. 1
, other than the board level subsystems
110
. The host controller
154
may be implemented as one of the boards
152
.
Each slot
151
has a unique binary identification or address that may be used to identify communications between the board
152
in a particular slot
151
and control devices such as a host computer
154
. Each slot
151
of the backplane
153
has a number of address pins (not shown) and each board
152
has a corresponding number of board pins (not shown). The address pins and board pins are connected to each other when a board
152
is plugged into a slot
151
and are used to communicate the slot address to circuitry on the board. Each address pin of the slot
151
, and the corresponding board pin on the board
152
, is used to communicate one bit of the slot address. For example, a backplane with twenty slots will require five address pins for each slot. For convenience, the board pins on the boards and the address pins in the backplane slots are sometimes called “bits” because each pin carries a binary signal.
Typically, the pins on the boards have pull-up resistors and each of the address pins in each backplane slot is either connected to circuit ground, or left unconnected to “float” to the supply voltage. The pattern of grounded and unconnected address pins is read by circuitry on the board as a corresponding pattern of 0's and 1's, which together represent the slot address of the board. For example, slot
1
of a backplane might have the four most significant bits grounded and the least significant bit floating, representing a binary value of “1.” A distinct pattern of grounded and unconnected address pins is used for each slot of the backplane so as to assign each slot a unique address. Preferably, the address pins in the slots are connected so as to assign addresses to the slots sequentially from a first value to a last value, such as from 1 to 20.
As illustrated in
FIG. 3
, some systems have two or more secondary backplanes
202
plugged into a primary backplane
203
. Each secondary backplane has multiple board slots
301
. Various boards
302
are plugged into the board slots (also called secondary backplane slots)
301
in the secondary backplanes
202
. For example, if there are three slots
201
in the primary backplane for receiving secondary backplanes
202
, and secondary backplanes
202
with ten slots each are plugged into the primary backplane
203
, the primary backplane can accommodate a total of thirty boards, instead of three.
Each board slot
301
in each secondary backplanes
202
must be uniquely identified by a board address. Furthermore it is desirable for those board addresses to progress sequentially in accordance with the physical positions of the slots
301
within a secondary backplane, and for the address ranges of the boards in neighboring secondary backplanes
302
to be contiguous—for example, if a first secondary backplane has board addresses
1
-
10
, the second secondary backplane preferably should have board addresses
11
-
20
. It would also be desirable to be able to use identical secondary backplanes in each of the available slots of the primary backplane so that any secondary backplane can be plugged into any slot of the primary backplane. The present invention is a method and apparatus for generating a contiguous, sequential set of board addresses for boards that are plugged into the board slots of a plurality of secondary backplanes, where the secondary backplanes are plugged into slots in a primary backplane.
It would also be desirable for each of the circuit boards
302
to be usable in any of the board slots
301
of the system, and thus for all of the circuit boards
302
to have identical address reading circuitry.
SUMMARY OF THE INVENTION
In summary, the present invention is an apparatus and method for providing addresses for boards plugged into slots in secondary backplanes, referred to as board slots. The secondary backplanes are in turn plugged into slots in a primary backplane, referred to as primary backplane slots. The addresses are unique for each board slot, and the range of addresses for each secondary backplane is contiguous with the range of addresses for a neighboring secondary backplane. The addresses are set as follows. Each slot in the primary backplane has one or more primary address pins. The primary address pins in the primary backplane slots are coupled so as to set the primary address pins in each primary backplane slot to a unique value. Each secondary backplane has a bus line for each primary address pin of the primary backplane slot into which it is plugged. The bus lines couple the primary address pins to board address identification pins, also called address pins, in certain of the board slots.
Address pins are provided for each board slot, and are set to selected values for each board slot. Some of the address pins in each slot are set to a 0 or 1 binary value by connecting those pins to ground or leaving the pins to float to the pull-up voltage on the board. Others of the address pins in each slot are set to values that depend on which primary backplane slot the secondary backplane is plugged into. More specifically, each of these address pins is coupled to a respective one of the bus lines so as to set that address pin to a value that is determined by the voltage on that bus line. The values of the address pins in the board slots are set so that the board addresses are contiguous from one secondary backplane to the next.
REFERENCES:
patent: 3872452 (1975-03-01), Stoops
patent: 4254473 (1981-03-01), Galdun et al.
patent: 5581787 (1996-12-01), Saeki et al.
patent: 5745708 (1998-04-01), Weppler et al.
Centigram Communications Corporation
Gaffin Jeffrey
Park Ilwoo
Pennie & Edmonds LLP
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