MRAM write apparatus and method

Details MRAM write apparatus and method MRAM write apparatus and method

2001-01-04

2002-02-26

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Systems using particular element

Magnetoresistive

C365S225700

Reexamination Certificate

active

06351409

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to the magnetoresistive type of information memories and more particularly to apparatus and methods of writing or programming magnetoresistive memories.
BACKGROUND OF THE INVENTION
The architecture for Magnetoresistive Random Access Memory (MRAM) is composed of a plurality or array of memory cells and a plurality of digit line and bit line intersections. The magnetoresistive memory cell generally used is composed of a magnetic tunnel junction (MTJ), an isolation transistor, and the intersection of digit and bit lines. It should be understood, however, that the present invention is not limited to MTJ cells and this type of cell and the associated circuitry is only used for exemplary purposes. The isolation transistor is generally a N-channel field effect transistor (FET). An interconnect stack connects the isolation transistor to the MTJ device, to the bit line, and to the digit line used to create part of the magnetic field for programming the MRAM cell.
MTJ memory cells generally include a non-magnetic conductor forming a lower electrical contact, a pinned magnetic layer, a tunnel barrier layer positioned on the pinned layer, and a free magnetic layer positioned on the tunnel barrier layer with an upper contact on the free magnetic layer.
The pinned layer of magnetic material has a magnetic vector that is always pointed in the same direction. The magnetic vector of the free layer is free, but constrained by the physical size of the layer and other anisotropies, to point in either of two directions. An MTJ cell is used by connecting it in a circuit such that electricity flows vertically through the cell from one of the layers to the other. The MTJ cell can be electrically represented as a resistor and the size of the resistance depends upon the orientation of the magnetic vectors. As is understood by those skilled in the art, the MTJ cell has a relatively high resistance when the magnetic vectors are misaligned (point in opposite directions) and a relatively low resistance when the magnetic vectors are aligned. Additional information as to the fabrication and operation of MTJ memory cells can be found in U.S. Pat. No. 5,702,831, entitled “Multi-Layer Magnetic Tunneling Junction Memory Cells”, issued Mar. 31, 1998, and incorporated herein by reference.
A bit line is generally associated with each column of an array of MTJ cells and a digit line is associated with each row of the array. The bit lines and digit lines are used to address individual cells in the array for both reading and writing or programming information in the array. Programming of a selected cell is accomplished by passing predetermined currents through the digit and bit lines intersecting at the selected cell. Several problems are prevalent in the standard memory architecture, including high programming currents and insufficient spacing between closely packed cells during programming.
Thus, it is desirable to provide improved MRAM memories and methods of programming that overcome these problems.


REFERENCES:
patent: 5946227 (1999-08-01), Naji
patent: 6163477 (2000-12-01), Tran
patent: 6205051 (2001-03-01), Brug et al.
patent: 6272040 (2001-08-01), Salter et al.
patent: 6285581 (2001-09-01), Tehrani et al.

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